| 1. |
- Bhide, Ameya, et al.
(författare)
-
Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs
- 2015
-
Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 62:7, s. 646-650
-
Tidskriftsartikel (refereegranskat)abstract
- Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.
|
|
| 2. |
- Ojani, Amin, et al.
(författare)
-
A DLL-based Injection-Locked Frequency Synthesizer for WiMedia UWB
- 2012
-
Ingår i: 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012). - : IEEE. - 9781467302180 - 9781467302197 ; , s. 2027-2030
-
Konferensbidrag (refereegranskat)abstract
- A WiMedia ultrawideband (UWB) frequency synthesizer is designed for band group #1. A very fast hopping is achieved by using a delay-locked loop (DLL) architecture which utilizes a novel variable gain voltage-controlled delay line (VCDL) scheme to compensate the phase error generated at the hopping instant. Fast-settling DLL allows an injection-locked oscillator (ILO) to be employed to reduce the current consumption in the edge combiner (EC). Simulated in STM 65-nm CMOS technology, synthesizer hopping time is less than two reference cycles. Phase noise at 3432 MHz is -124 dBc/Hz at 1 MHz offset. The adjacent spur level from the Monte Carlo simulation is -34 dBc. Excluding CML divider, the synthesizer draws 6.7 mW from a 1.2 V supply.
|
|
| 3. |
- Ojani, Amin, et al.
(författare)
-
A Low-Power Direct IQ Upconversion Technique Based on Duty-Cycled Multi-Phase Sub-Harmonic Passive Mixers for UWB Transmitters
- 2014
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a low-power direct-conversion IQ modulator for ultra-wideband (UWB) communications based on multi-phase duty-cycled sub-harmonic passive mixers. The novelty of the proposed architecture is in employing a quadrature mixer array in such a configuration that the upconvertion of the baseband signal can be performed using a much lower LO frequency, i.e., a sub-harmonic frequency of the carrier. As a result, several benefits can be gained. Requiring a sub-harmonic LO (SHLO) relaxes the requirements on the frequency synthesizer circuitry. Moreover, the need for digital power-hungry or analog inductor-based high frequency LO buffers is alleviated. In addition, since rail-to-rail LO signals can be provided easier and with less power consumption at lower frequencies, we can employ passive mixers in the mixer array to improve the power consumption and linearity of the overall transmitter. Multi-phase LO clocks required by the proposed scheme are provided using a delay-locked loops (DLL). The proposed architecture is utilized in design of a WiMedia-UWB direct-conversion TX in a standard 65-nm CMOS technology. The MC simulation results indicate LO leakage of –68 dBc and sideband rejection of –39 dBc. The overall system draw 6.8 mA from a 1.2 V supply.
|
|
| 4. |
- Ojani, Amin, et al.
(författare)
-
A Process Variation Tolerant DLL-Based UWB Frequency Synthesizer
- 2012
-
Ingår i: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS). - : IEEE. - 9781467325257 - 9781467325264 ; , s. 558-561
-
Konferensbidrag (refereegranskat)abstract
- A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.
|
|
| 5. |
- Ojani, Amin, et al.
(författare)
-
A quadrature UWB frequency synthesizer with dynamic settling-time calibration
- 2013
-
Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE. - 9781467357609 ; , s. 2480-2483
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a quadrature DLL-based architecture for WiMedia ultra-wideband (UWB) frequency synthesis. I and Q carriers are directly generated by combining the quadrature multi-phase outputs of the DLL, using separate edge combiners (EC). A variable-stage voltage-controlled delay line (VCDL) scheme is proposed to provide the corresponding output phases to each EC, without the need for multiplexing the DLL outputs for different bands. Moreover, to prevent possible synthesizer hopping time degradation due to dynamic variations in temperature and voltage, a monitoring mechanism is employed to measure the time error at the instant of band switching, and compensate for it if it is beyond a limited value. The Synthesizer is implemented in a standard 65-nm CMOS technology and the simulation results indicate a hopping time of 4.5 to 8.8 ns across process corners. Simulated phase noise at 1 MHz offset from 4488 MHz carrier is -115 dBc/Hz and the worst case spur suppression is -31 dBc. The synthesizer consumes 13.9 mA from a 1.2-V supply.
|
|
| 6. |
- Ojani, Amin, et al.
(författare)
-
A Self-Calibration Technique for Fast-Switching Frequency-Hopped UWB Synthesis
- 2014
-
Ingår i: Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014. - : IEEE. - 9788363578039 ; , s. 154-159
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a self-calibration technique for a fast-switching DLL-based frequency synthesizer targeting frequency-hopped ultra-wideband (UWB) communication. The proposed architecture employs the concept of track-and-hold (T/H) technique to sample the lock control voltages regarding each channel and store them across a corresponding capacitor during a start-up phase. During the normal operation when the hopping command arrives, the stored voltages are applied to the loop in an open-loop regime to perform fast channel switching of sub-9.5 ns which is required by WiMedia-UWB standard. Certain architectural and circuit methods are utilized in order to minimize the error in the sampled voltages caused by channel charge injection and clock feedthrough of the sampling switches. Since the proposed fast-switching scheme does not require a wide loop bandwidth, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples resulting in sideband spurs is eliminated. Moreover, the VCDL can be biased in the low-gain region of its transfer function to reduce its noise transfer to the synthesizer output. The proposed architecture is implemented in a 65-nm standard CMOS process and the simulation results indicate a worst-case band switching time of less than 5.5 ns.
|
|
| 7. |
- Ojani, Amin
(författare)
-
Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication
- 2014
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Ever increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 ‒ 10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer’s sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLLbased architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equally-spaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stage-delay mismatch, the static phase error of the locked-loop, and the duty cycle distortion of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer’s spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer’s behavioral and transistor-level model ina 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieved by introducing an openloop compensation technique to keep the total delay-length of the delay line unchanged at the instant of band hopping. The relation between the compensation accuracy and the hopping speed is analyzed and formulated. In addition, to make the technique immune to process-voltage-temperature (PVT) variations, two calibration techniques are introduced. Furthermore, injection-locking technique is employed to reduce the total current consumption in the EC. The presented concept is supported by measurement results on a test chip implemented in a 65-nm CMOS process and achieves a worst-case sideband spur of ‒44 dBc and dissipates 21 mW of power at 1.2 V supply voltage.The second DLL-based synthesizer employs the concept of track-and-hold (T/H) technique to sample the lock control voltages and store them across the corresponding capacitors during a start-up phase. In normal operation, the loop control voltage is pre-charged to the corresponding stored voltage to perform fast channel switching. Since the presented architecture does not rely on the DLL bandwidth for fast switching, the existing tradeoff in phase-locked systems between the settling time and the control voltage ripples (which result in sideband spurs) is eliminated. Also, the delay line can be biased in low gain regions of its transfer function to reduce its noise amplification.The third DLL-based architecture merges the edge-combing and upconversion operations to achieve a low-power direct conversion IQ modulator based on subharmonic passive mixers and multiphase duty-cycled LO. The novelty of the architecture is in employing a quadrature mixer array in such a configuration that the upconversion of the baseband signal can be performed at a sub-harmonic of the LO. Therefore, the requirements on the frequency synthesizer circuitries and LO buffers are relaxed. In addition, since rail-to-rail clocks are provided easier at such low subharmonic frequencies, passive mixers are employed to further reduce the power dissipation and improve the linearity of the overall transmitter. Multiphase subharmonic LO clocks required by the proposed scheme are provided using a quadrature edge-combining DLL.
|
|
| 8. |
- Ojani, Amin, et al.
(författare)
-
Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers
- 2014
-
Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 61:11, s. 3075-3084
-
Tidskriftsartikel (refereegranskat)abstract
- Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.
|
|
| 9. |
- Ojani, Amin, et al.
(författare)
-
Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers
- 2015
-
Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 62:1, s. 273-282
-
Tidskriftsartikel (refereegranskat)abstract
- Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.
|
|
| 10. |
- Payami, Sima, et al.
(författare)
-
An operational amplifier for high performance pipelined ADCs in 65nm CMOS
- 2012
-
Konferensbidrag (refereegranskat)abstract
- A CMOS fully differential high gain-bandwidth (GBW) product operational amplifier (OpAmp) is presented in this paper. In order to achieve a high gain, the Nested gain-boosting technique [1] is employed. The design is implemented in a 1.1V standard 65nm CMOS process. The DC-gain of the OpAmp is larger than 77.9dB with the unity-gain frequency of 4.61GHz while achieving 76.2 degrees of phase margin (PM). Applying the maximum input swing, the output signal settles to 0.01% accuracy in less than 3.8ns. The output total harmonic distortion (THD) of the OpAmp is 0.586% for maximum signal swing at the frequencies near Nyquist frequency with the input-referred noise of 5.4nV/√Hz. The high GBW product of this design makes it suitable for 12-bit 200MS/s pipelined ADC applications.
|
|
