| 1. |
- Malm, Gunnar, 1972-, et al.
(författare)
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Low-frequency noise in FinFETs with PtSi Schottky-barrier source/drain contacts
- 2011
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Ingår i: Proceedings of the IEEE 21st International Conference on Noise and Fluctuations, ICNF 2011. - : IEEE Computer Society. - 9781457701924 ; , s. 135-138
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Konferensbidrag (refereegranskat)abstract
- Schottky-barrier source/drain (SB-S/D) is a promising solution for low-resistive contact formation in fully depleted SOI ultra-thin body (UTB) FETs, or FinFETs. In this study the low-frequency noise of FinFETs and UTB-FETs, with platinum-silicide based source/drain contacts with low barrier height was characterized. The barrier height was tuned by means of segregation of implanted As or B. In the linear region of operation the noise power spectral density of devices with different barrier heights was not significantly affected for a given drain current. This suggests that channel noise dominates the behavior and that the low effective Schottky barrier height in dopant segregated devices does not introduce additional noise.
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| 2. |
- Olyaei, Maryam, et al.
(författare)
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A study of low-frequency noise on high-k/metal gate stacks with in situ SiOx interfacial layer
- 2013
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Ingår i: 2013 22nd International Conference on Noise and Fluctuations, ICNF 2013. - New York : IEEE conference proceedings. - 9781479906680 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Low-frequency noise of HfO2/TiN nMOSFETs with different SiO x interfacial layer (IL) thicknesses is presented. It is observed that chemically formed thin ILs (0.4 nm, 0.45 nm and 0.5 nm) show a noise level close to a reference thermal IL(1 nm). This is shown to relate to the dominant contribution of the high-k HfO2 traps in comparison to the IL traps. The average extracted values for effective trap densities in these wafers are Nt= 7×1018, 1×1019, 2×10 19 and 4.8×1019 for thermal oxide, 0.5 nm, 0.45 nm and 0.4 nm chemical oxide wafers respectively.
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| 3. |
- Olyaei, Maryam, et al.
(författare)
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Improved Low-frequency Noise for 0.3nm EOT Thulium Silicate Interfacial Layer
- 2014
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Ingår i: Solid State Device Research Conference (ESSDERC), 2014 44th European. - : IEEE conference proceedings. - 9781479943760 ; , s. 361-364
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Konferensbidrag (refereegranskat)abstract
- Low-frequency noise (LFN) of gate stacks with Tm2O3 high-k dielectric and thulium silicate (TmSiO) interfacial layer (IL) is investigated. The measured 1/f noise is compared to SiOx/HfO2 stacks with comparable IL thickness. Integration of a high-k thulium silicate IL provides a scaled EOT of 0.3nm with good mobility and interface quality, hence excellent LFN is obtained. The LFN noise for devices with TmSiO/Tm2O3 gate dielectric is reduced for nMOSFETs and comparable for pMOSFETs compared to SiOx/HfO2 devices.
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| 4. |
- Olyaei, Maryam, et al.
(författare)
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Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs
- 2015
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Ingår i: IEEE Electron Device Letters. - : IEEE Press. - 0741-3106 .- 1558-0563. ; 36:12, s. 1355-1358
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Tidskriftsartikel (refereegranskat)abstract
- Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3nm EOT interfacial layer (TmSiO) and two different bulk high-k dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate stack EOT was 1.2 nm and 0.65 nm for the Tm2O3 and HfO2 samples respectively. In general both gate stacks resulted in 1/f type of noise spectra and noise levels comparable to conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was 2.5×1017 cm-3eV-1 and 1.5×1017 cm-3eV-1 for TmSiO/HfO2 and TmSiO/Tm2O3 respectively. Therefore the best noise performance was observed for the gate stack with Tm2O3 bulk high-k layer and we suggest that the interface free single layer ALD fabrication scheme could explain this.
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| 5. |
- Olyaei, Maryam
(författare)
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Low-frequency noise in high-k gate stacks with interfacial layer engineering
- 2015
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The rapid progress of complementary-metal-oxide-semiconductor (CMOS) integrated circuit technology became feasible through continuous device scaling. The implementation of high-k/metal gates had a significantcontribution to this progress during the last decade. However, there are still challenges regarding the reliability of these devices. One of the main issues is the escalating 1/fnoise level, which leads to degradation of signal-to-noise ratio (SNR) in electronic circuits. The focus of this thesis is on low-frequency noise characterization and modeling of various novel CMOS devices. The devices include PtSi Schottky-barriers for source/drain contactsand different high-kgatestacksusingHfO2, LaLuO3 and Tm2O3 with different interlayers. These devices vary in the high-k material, high-k thickness, high-k deposition method and interlayermaterial. Comprehensive electrical characterization and low-frequency noise characterization were performed on various devices at different operating conditions. The noise results were analyzed and models were suggested in order to investigate the origin of 1/f noise in these devices. Moreover, the results were compared to state-of-the-art devices.High constant dielectrics limit the leakage current by offering a higher physical dielectric thickness while keeping the Equivalent Oxide Thickness (EOT) low. Yet, the 1/f noise increases due to higher number of traps in the dielectric and also deterioration of the interface with silicon compared to SiO2. Therefore, in order to improve the interface quality, applying an interfacial layer (IL) between the high-k layer and silicon is inevitable. Very thin, uniform insitu fabricated SiO2 interlayers with HfO2 high-k dielectric have been characterized. The required thickness of SiO2 as IL for further scaling has now reached below 0.5 nm. Thus, one of the main challenges at the current technology node is engineering the interfacial layer in order to achieve both high quality interface and low EOT. High-k ILs are therefore proposed to substitute SiOx dielectrics to fulfill this need. In this work, we have made the first experiments on low-frequency noise studies on TmSiO as a high-k interlayer with Tm2O3 or HfO2 on top as high-k dielectric. The TmSiO/Tm2O3 shows a lower level of noise which is suggested to be related to smoother interface between the TmSiO and Tm2O3. We have achieved excellentnoise performancefor TmSiO/Tm2O3 and TmSiO/HfO2 gate stacks which are comparableto state-of-the-art SiO2/HfO2 gate stacks.
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| 6. |
- Olyaei, Maryam, et al.
(författare)
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Low-frequency Noise in High-k LaLuO3/TiN MOSFETs
- 2011
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Ingår i: 2011 International Semiconductor Device Research Symposium (ISDRS). ; , s. TA01-TA04
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Konferensbidrag (refereegranskat)abstract
- The implementation of high-k gate stacks has enabled further scaling in CMOS technology. However it is still challenging due to increased number of trap densities appeared at the high-k interface or in the bulk, mobility degradation and enhancement in the level of low-frequency noise [1]. Previously low-frequency noise in devices with PtSi Schottky-barrier source/drain contacts were studied [2]. In this work the low-frequency noise characterization of MOSFETs with high-k LaLuO3 dielectric and TiN gate is presented. The devices were fabricated on an SOI substrate thinned down to 30 nm by sacrificial dry oxidation and HF wet etching. Active areas were patterned through MESA etching. The process was continued with an optional growth of a 5 nm layer of thermal oxide on the wafers. The high-k LaLuO3 dielectric was deposited by MBE (tLaLuO3=6 nm) and the metal TiN gate by sputtering (tTiN=20 nm). This was followed by in-situ deposition of phosphorus doped poly-Si with tpoly=150 nm. For the reference wafer, the high-k deposition was skipped. PtSi Schottky-barrier source/drain with Boron and Arsenic implantation was carried out for pMOSFETs and nMOSFETs respectively. In the next step, RTA at 700°C was performed for dopant segregation at the PtSi/Si interface. The fabrication process was finalized by metallization and FGA (10% H2 in N2 at 400° C for 30 min).
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| 7. |
- Olyaei, Maryam, et al.
(författare)
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Low-Frequency Noise in High-k LaLuO3/TiN MOSFETs
- 2012
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Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 78:SI, s. 51-55
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Tidskriftsartikel (refereegranskat)abstract
- Low-frequency noise (LFN) characterization of high-k LaLuO3/TiN nMOS transistors is presented. The experimental results including the noise spectrum and normalized power noise density and mobility are reported. The noise results were successfully modeled to the correlated number and mobility fluctuation noise equation. High-k dielectric devices show lower mobility and roughly one to two orders of magnitude higher low-frequency noise which is comparable to the hafnium based oxide layers. The implementation of higher-k LaLuO3 seems to be a suitable candidate to the trade-off between equivalent oxide thickness scaling and low frequency noise.
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| 8. |
- Östling, Mikael, et al.
(författare)
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Atomic layer deposition-based interface engineering for high-k/metal gate stacks
- 2012
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Ingår i: ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. - : IEEE. - 9781467324724 ; , s. 6467643-
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Konferensbidrag (refereegranskat)abstract
- This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide (Al2O3), Lanthanum-Lutetium-Oxide (LaLuO3) and Lanthanum-Oxide (La 2O3) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed.
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