| 1. |
- Czernohorsky, M., et al.
(författare)
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Stability of crystalline Gd(2)O(3) thin films on silicon during rapid thermal annealing
- 2008
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Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 23:3, s. 035010-
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd(2)O(3) layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack ( silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 degrees C anneal.
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| 2. |
- Gottlob, H. D. B., et al.
(författare)
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0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
- 2006
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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| 3. |
- Gottlob, H. D. B., et al.
(författare)
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CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
- 2006
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
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Tidskriftsartikel (refereegranskat)abstract
- Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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| 4. |
- Lemme, Max C., 1970-, et al.
(författare)
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Complementary metal oxide semiconductor integration of epitaxial Gd(2)O(3)
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:1, s. 258-261
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, epitaxial gadolinium oxide (Gd(2)O(3)) is reviewed as a potential high-K gate dielectric, both "as deposited" by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a "gentle" replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd(2)O(3) gate dielectrics is explored by carefully controlling the annealing conditions.
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| 5. |
- Nazarov, A. N., et al.
(författare)
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Charge trapping in ultrathin Gd2O3 high-k dielectric
- 2007
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:9-10, s. 1968-1971
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Tidskriftsartikel (refereegranskat)abstract
- Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 x 10(-20) cm(2). The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 x 10(12) eV(-1) cm(-2) near the valence band edge.
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| 6. |
- Raeissi, Bahman, 1979, et al.
(författare)
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High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2007
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Ingår i: ESSDERC 2007. - 9781424411238 ; , s. 283-286
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Konferensbidrag (refereegranskat)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd(2)O(3) prepared by MBE and ALD, and for HfO(2) prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.
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| 7. |
- Raeissi, Bahman, 1979, et al.
(författare)
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High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
- 2008
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:9, s. 1274-1279
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Tidskriftsartikel (refereegranskat)abstract
- Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 preparedby molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO2 prepared byreactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance.The capture cross sections are found to be thermally activated and to increase steeply with theenergy depth of the interface electron states. The methodology adopted is considered useful for increasingthe understanding of high-k-oxide/silicon interfaces.
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