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- Bertozzi, Davide, et al.
(författare)
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Networks-on-Chip : Emerging Research Topics and Novel Ideas (Editorial)
- 2007
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Ingår i: VLSI design (Print). - : Hindawi Limited. - 1065-514X .- 1563-5171. ; 2007, s. ID: 26454-
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Tidskriftsartikel (populärvet., debatt m.m.)abstract
- Network-on-chip- (NoC-) based application-specific systems on chip, where information traffic is heterogeneous and delay requirements may largely vary, require individual capacity assignment for each link in the NoC. This is in contrast to the standard approach of on- and off-chip interconnection networks which employ uniform-capacity links. Therefore, the allocation of link capacities is an essential step in the automated design process of NoC-based systems. The algorithm should minimize the communication resource costs under Quality-of-Service timing constraints. This paper presents a novel analytical delay model for virtual channeled wormhole networks with nonuniform links and applies the analysis in devising an efficient capacity allocation algorithm which assigns link capacities such that packet delay requirements for each flow are satisfied.
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- Chen, Kun-Chih, et al.
(författare)
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Guest Editorial : Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators
- 2020
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2156-3357 .- 2156-3365. ; 10:3, s. 265-267
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to investigate the latest research about the topic of communication-aware AI subsystems and accelerators. Because of the complex communication, extensive computations, and massive storage requirements, the demand of communication-aware AI designs has been increased in recent years.
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| 6. |
- Daneshtalab, Masoud, et al.
(författare)
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Special issue on many-core embedded systems
- 2014
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Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 38:6, s. 525-525
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 8. |
- Holsmark, Rickard, et al.
(författare)
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A Multi-Level Routing Scheme and Router Architecture to support Hierarchical Routing in Large Network on Chip Platforms
- 2010
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Ingår i: 4th Workshop on Highly Parallel Processing on a Chip (HPPC 2010).
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Konferensbidrag (refereegranskat)abstract
- The concept of hierarchical networks is useful for designing a large heterogeneous NoC by reusing predesigned small NoCs as subnets. It can also be helpful when analyzing and designing a large NoC as interconnection of subnets at a higher level of abstraction. Hierarchical deadlock-free routing is required to enable deadlock-free interconnection of sub-networks with different internal routing algorithms. In this paper we show that multi-level addressing is a cost-effective implementation option for hierarchical deadlock-free routing. We propose a two-level routing scheme, which is not only efficient, but also enables co-existence of algorithmic and table-based implementation in one router. A hierarchical view of the network simplifies addressing of network nodes and address decoding in the router. Synthesis results show that a 2-level hierarchical router design for an 8x8 NoC, can reduce area and power requirements by up to ~20%, as compared to a router for the flat network. This work also proposes a new possibility for increasing the number of nodes available for subnet-to-subnet interfaces, while keeping the properties of hierarchical deadlock-freedom. We evaluate and discuss the communication performance in a 2-level hierarchical network for various subnet interface set-ups and traffic situations. A cycle accurate simulator has been developed and used for this purpose.
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| 9. |
- Holsmark, Rickard, et al.
(författare)
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Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
- 2008
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Ingår i: Journal of systems architecture. - : Elsevier BV. - 1383-7621 .- 1873-6165. ; 54:3-4, s. 427-440
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Tidskriftsartikel (refereegranskat)abstract
- The simplicity of regular mesh topology NoC architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the tile size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology can not ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the tile size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers.
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| 10. |
- Holsmark, Rickard, et al.
(författare)
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Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
- 2006
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Ingår i: 9th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools. Croatia, Sept 2006. - 0769526098
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Konferensbidrag (refereegranskat)abstract
- Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as provides new design issues and challenges. The most important among these is the design of a deadlock free routing algorithm. In this paper, we present and compare two routing algorithms for mesh topology NoC with regions. The first algorithm is borrowed from the area of fault tolerant networks and is adapted for the NoC context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases.
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