| 1. |
- Fischer, Andreas C., 1982-, et al.
(författare)
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Wire-bonded through-silicon vias with low capacitive substrate coupling
- 2011
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Ingår i: Journal of Micromechanics and Microengineering. - : IOP Science. - 0960-1317 .- 1361-6439. ; 21:8, s. 085035-
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Tidskriftsartikel (refereegranskat)abstract
- Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.
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| 2. |
- Grange, Matt, et al.
(författare)
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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
- 2009
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Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
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Konferensbidrag (refereegranskat)abstract
- The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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| 3. |
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| 4. |
- Pamunuwa, D., et al.
(författare)
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Maximizing throughput over parallel wire structures in the deep submicrometer regime
- 2003
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 11:2, s. 224-243
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Tidskriftsartikel (refereegranskat)abstract
- In a parallel multiwire structure, the exact spacing and size of the wires determine both the resistance and the distribution of the capacitance between the ground plane and the adjacent signal carrying conductors, and have a direct effect on the delay. Using closed-form equations that map the geometry to the wire parasitics and empirical switch factor based delay models that show how repeaters can be optimized to compensate for dynamic effects, we devise a method of analysis for optimizing throughput over a given metal area. This analysis is used to show that there is a clear optimum configuration for the wires which maximizes the total bandwidth. Additionally, closed form equations are derived, the roots of which give close to optimal solutions. It is shown that for wide buses, the optimal wire width and spacing are independent of the total width of the bus, allowing easy optimization of on-chip buses. Our analysis and results are valid for lossy interconnects as are typical of wires in sub-micron technologies.
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| 5. |
- Pamunuwa, D., et al.
(författare)
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Modelling noise and delay in VLSI circuits
- 2003
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Ingår i: Electronics Letters. - : Institution of Engineering and Technology (IET). - 0013-5194 .- 1350-911X. ; 39:3, s. 269-271
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Tidskriftsartikel (refereegranskat)abstract
- New models for estimating delay and noise in VLSI circuits, based on closed form expressions for the first and second moment of the impulse response in coupled RC trees are reported. The effect of crosstalk on delay and noise can be accurately estimated with a complexity only marginally higher than the Elmore delay.
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| 6. |
- Rana, Sunil, et al.
(författare)
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Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory
- 2020
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Ingår i: Nature Communications. - : Nature Publishing Group. - 2041-1723. ; 11:1
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Tidskriftsartikel (refereegranskat)abstract
- Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 °C.
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| 7. |
- Weerasekera, Roshan, et al.
(författare)
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Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime
- 2006
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Ingår i: Int. Workshop Syst. Level Interconnect Predict. SLIP. - New York, NY, USA : ACM. - 1595932550 - 9781595932556 ; , s. 113-120
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Konferensbidrag (refereegranskat)abstract
- In this paper we propose a smart repeater that consumes less energy and is suitable for driving global interconnections in nanometre technologies. When there is coupling between interconnects, the effective capacitance of a given wire is a function not only of the physical geometry, but also the relative switching pattern described by the bits on the wire in question (the victim) and the adjacent wires (aggressors). The drive strength of a traditional repeater is static, resulting in a spread of the propagation delay, with the repeater strength being essentially too much for every bit pattern other than the worst-case pattern. In the proposed SMART repeater, the drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. By disconnecting part of the repeater when it is not needed, the total load capacitance to the previous stage is reduced, resulting in reduced energy consumption for those instances. It is shown that the potential average saving in energy can be as much 15% with a 18% jitter reduction over a traditional repeater for typical global wire lengths in nanometre technologies.
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| 8. |
- Weldezion, Awet Yemane, et al.
(författare)
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A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns
- 2013
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Ingår i: 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013. - : IEEE. - 9781467364843 ; , s. 6702365-
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Konferensbidrag (refereegranskat)abstract
- This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.
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