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| 2. |
- Grange, Matt, et al.
(författare)
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Examination of Delay and Signal Integrity Metrics in Through Silicon Vias
- 2009
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Ingår i: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test, Electronic Workshop Digest, Palais des Congrès Acropolis – Nice, France, Friday April 24, 2009. - Nice, France. ; , s. 260-264
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Konferensbidrag (refereegranskat)abstract
- This article discusses results from simulations of signaling in Through Silicon Vias (TSVs) with an emphasis on latency and signal integrity effects. Data from field solver simulations is used for TSV parasitics and employed in SPICE simulations. A reduced order electrical circuit is proposed for lone TSVs as well as bundled structures and switch-factor based delay models are derived to calculate rise times in a 3x3 bundle. Furthermore Signal Integrity (SI) issues in coupled TSVs are briefly discussed.
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| 3. |
- Grange, Matt, et al.
(författare)
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Modeling the Computational Efficiency of 2-D and 3-D Silicon Processors for Early-Chip Planning
- 2011
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Ingår i: 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). - 9781457713989 - 9781457713996 ; , s. 310-317
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Konferensbidrag (refereegranskat)abstract
- Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.
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| 4. |
- Grange, Matt, et al.
(författare)
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Modeling the Efficiency of Stacked Silicon Systems : Computational, Thermal and Electrical Performance
- 2011
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Konferensbidrag (refereegranskat)abstract
- Technological advances in processor design have typically reliedon scaling feature size and frequency. Recently however, many new design choiceshave emerged partly due to the slowing of scaling:– Many-core architectures arebeginning to replace single-core ICs to circumvent 2-D bottlenecks, The number ofI/Os are on the rise, so the cost of off-chip transactions is becoming heftier. Moreover,3-D Integration may provide further performance benefits without investment in lowertechnology nodes. Understanding these trade-offs can provide guidelines to optimizethe architecture of future systems under performance, thermal and cost constraints.We have constructed a model and tool that assesses computational efficiency underthese criteria.
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| 5. |
- Grange, Matt, et al.
(författare)
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Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
- 2011
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Ingår i: NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. - New York, NY, USA : ACM Digital Library. ; , s. 57-64
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Konferensbidrag (refereegranskat)abstract
- A general expression for the average distance for meshes of any dimension and radix, including unequal radices in different dimensions, valid for any traffic pattern under zero-load condition is formulated rigorously to allow its calculation without network-level simulations. The average distance expression is solved analytically for uniform random traffic and for a set of local random traffic patterns. Hot spot traffic patterns are also considered and the formula is empirically validated by cycle true simulations for uniform random, local, and hot spot traffic. Moreover, a methodology to attain closed-form solutions for other traffic patterns is detailed. Furthermore, the model is applied to guide design decisions. Specifically, we show that the model can predict the optimal 3-D topology for uniform and local traffic patterns. It can also predict the optimal placement of hot spots in the network. The fidelity of the approach in suggesting the correct design choices even for loaded and congested networks is surprising. For those cases we studied empirically it is 100%.
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| 6. |
- Grange, Matt, et al.
(författare)
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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
- 2009
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Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
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Konferensbidrag (refereegranskat)abstract
- The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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| 7. |
- Jantsch, Axel, et al.
(författare)
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The Promises and Limitations of 3-D Integration
- 2011
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Ingår i: 3D Integration for NoC-based SoC Architectures. - New York, NY : Springer Publishing Company. ; , s. 27-44
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- The intrinsic computational efficiency (ICE) of silicon defines the upper limit of the amount of computation within a given technology and power envelope. The effective computational efficiency (ECE) and the effective computational density (ECD) of silicon, by taking computation, memory and communication into account, offer a more realistic upper bound for computation of a given technology. Among other factors, they consider how distributed the memory is, how much area is occupied by computation, memory and interconnect, and the geometric properties of 3-D stacked technology with through silicon vias (TSV) as vertical links. We use ECE and ECD to study the limits of performance under different memory distribution constraints of various 2-D and 3-D topologies, in current and future technology nodes. Among other results, our model shows that in a 35 nm technology a 16 stack 3-D system can, as a theoretical upper limit, obtain 3.4 times the performance of a 2-D system (8.8 Tera OPS vs 2.6 TOPS) at 70% reduced frequency (2.1 vs 3.7 GHz) on 1/8 the total area (50 vs 400 mm2).
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| 8. |
- Li, Yingying, 1994-, et al.
(författare)
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Design and fabrication of a 4-terminal in-plane nanoelectromechanical relay
- 2023
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Konferensbidrag (refereegranskat)abstract
- We present 4-terminal (4-T) silicon (Si) nanoelectronmechanical (NEM) relays fabricated on silicon-oninsulator (SOI) wafers. We demonstrate true 4-T switching behavior with isolated control and signal paths. A pull-in voltage as low as 11.6 V is achieved with the miniaturized design. 4-T NEM relays are a very promising candidate for building ultra-low-power logic circuits since they enable novel circuit architectures to realize logic functions with far fewer devices than CMOS implementations, while also allowing the dynamic power consumption to be reduced by body-biasing.
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| 9. |
- Li, Yingying, 1994-, et al.
(författare)
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Integrated 4-terminal single-contact nanoelectromechanical relays implemented in a silicon-on-insulator foundry process
- 2023
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Ingår i: Nanoscale. - : Royal Society of Chemistry. - 2040-3364 .- 2040-3372.
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Tidskriftsartikel (refereegranskat)abstract
- Integrated nanoelectromechanical (NEM) relays can be used instead of transistors to implement ultra-low power logic circuits, due to their abrupt turn-off characteristics and zero off-state leakage. Further, realizing circuits with 4-terminal (4-T) NEM relays enables significant reduction in circuit device count compared to conventional transistor circuits. For practical 4-T NEM circuits, however, the relays need to be miniaturized and integrated with high-density back-end-of-line (BEOL) interconnects, which is challenging and has not been realized to date. Here, we present electrostatically actuated silicon 4-T NEM relays that are integrated with multi-layer BEOL metal interconnects, implemented using a commercial silicon-on-insulator (SOI) foundry process. We demonstrate 4-T switching and the use of body-biasing to reduce pull-in voltage of a relay with a 300 nm airgap, from 15.8 V to 7.8 V, consistent with predictions of the finite-element model. Our 4-T NEM relay technology enables new possibilities for realizing NEM-based circuits for applications demanding harsh environment computation and zero standby power, in industries such as automotive, Internet-of-Things, and aerospace.
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| 10. |
- Nurmi, T., et al.
(författare)
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Global interconnect analysis
- 2005
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Ingår i: Interconnect-Centric Design for Advanced SoC and NoC. - Boston : Springer Science+Business Media B.V.. - 9781402078354 - 9781402078361 ; , s. 55-84
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Bokkapitel (refereegranskat)abstract
- The rapid development in deep submicron (DSM) technology makes possible to design complex billion-transistor chips. To take full advantage of increased integration density and cope with the difficulties in designing such complex systems, the emphasis of design methodology has changed from gate-level design to the exploitation of intellectual property (IP) blocks. This IP-based design is rapidly becoming the dominating design paradigm in System-on-Chip (SoC) era. IP blocks themselves are usually verified by the supplier for some technology node but the problem is how to ensure the correct performance when the IP block is integrated in the SoC or even in Network-on-Chip (NoC) environment. The problems occur in adapting the block interface into the used communication frame. The main objective is to make computation (IP blocks) and communication independent on each other. Due to increasing integration density and diminishing wire dimensions, communication using traditional SoC interconnect schemes (such as buses) does not scale up properly compared with system complexity. This leads to the communication scheme where traditional buses and their arbitration are replaced with network switches connecting various IP blocks in different network nodes to each other. Thus, a shift from SoC to NoC is predicted when system complexity scales up on chip level. Network nodes bring inherent pipelining and buffering onto system level which is important when dealing with global wires that have more resistive and inductive nature in current and future DSM technologies. Additionally, undesired transmission errors can be reduced with errorchecking, e.g. in each network node. In this case, latency may increase as a result of increased reliability. In this chapter, we first discuss parasitic modeling in the presence of crosstalk and delay modeling of global wires. Inductance issues are discussed in more detail in chapter 5 and thus we omit them here. Some possible interconnect schemes in SoC and NoC are shortly discussed. In section 3.3 we evaluate cost functions (e.g. power consumption and area) that IP blocks set for the global communication network. We present a method how to evaluate those costs in the early phase of design. By evaluating costs of those resources we can better optimize global interconnects to meet both signal and power distribution challenges. We present one case study example on the cost evaluation. Finally, in section 3.4 we apply methods and theories presented in earlier sections and optimize global interconnects to meet different constraints. The delay in global wires is optimized using repeaters that are sized properly and placed in proper distances so that the overall delay is optimized. Then we present optimal signaling having maximum throughput as a constraint. Last, we present a case study in which both power and signal distribution are simultaneously optimized. This is done by using a method called interconnect partitioning and the design constraint in this case is the maximum allowed variation of power supply levels in the power distribution network. The variation depends on the grain size of the power distribution grid and power consumption taking place in IP (or functional) blocks due to simultaneous switching of large amount of logic gates in a very short time interval.
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