| 1. |
- Garrido Gálvez, Mario, et al.
(författare)
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A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals
- 2018
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 65:11, s. 1693-1697
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 log(2) N - 2 real adders, log(2) N - 2 real multipliers, and N + 9 log(2) N - 19 real delay elements, where N represents the size of the FFT.
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| 2. |
- Garrido, Mario, 1981-, et al.
(författare)
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A Pipelined FFT Architecture for Real-Valued Signals
- 2009
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 56:12, s. 2634-2643
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.
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| 3. |
- Gustafsson, Oscar, 1973-
(författare)
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Contributions to low-complexity digital filters
- 2003
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In this thesis we discuss design and implementation of low-complexity digital filters. Digital filters are key components in many digital signal processing (DSP) systems. Typical applications include interpolation, decimation, and noise suppression.The work presented in the thesis can be divided into four parts.In the first part, we consider implementation of wave digital filters using bit-and digit-serial arithmetic. Scheduling formulations to obtain maximally fast (or rate optimal) implementations are presented for a number of lattice wave digital filters. By using a numerically equivalent state-space representation a similar approach is introduced for ladder wave digital filters. It is shown that maximally fast implementations also can be obtained using distributed arithmetic. Furthermore, the optimal degree of logic level pipelining is derived for maximal sample rate.In the second part, a novel class of frequency-response masking filters is introduced. The filter structures use identical subfilters and, thereby, a lowcomplexity, pipeline/interleaved, implementation can be obtained using folding. By using frequency-response masking techniques the number of multipliers required is decreased for FIR filters and the maximal sample rate is increased for IIR filters. The problems of single and multiple constant multiplication (SCM and MCM) are discussed in the third part. When the multiplication coefficient is constant it is possible to reduce the number of additions required compared to a general coefficient multiplication. Furthermore, it is possible to utilize redundant subexpressions when one data is multiplied with multiple constant coefficients. For the single multiplier case, a novel graph formulation is introduced that decreases the search space required for optimum design. For the MCM problem two novel solutions are introduced. One is based on integer linear programming (ILP) and can be integrated with the design of linear- phase FIR filters. The other is based on minimum spanning trees (MSTs) and, as such, the solution time is polynomial in the number of coefficients. Furthermore, both the SCM and MCM problems are considered using high-speed redundant carry-save adders, and solutions are proposed.Finally, in the fourth part, the design of linear-phase FIR filters using mixed integer linear programming (MILP) is discussed. Here, we minimize the arithmetic complexity given a filter specification. Problems are formulated for minimum number of signed-power-of-two (SPT) terms in the coefficients, minimum number of adders in the complete filter, and minimum total Hamming distance between adjacent coefficients. The last approach is suitable for low-power implementation on multiply-and-accumulate (MAC) architectures, e.g., DSP processors.
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