| 1. |
- Zhang, Ying, et al.
(författare)
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Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip
- 2023
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Ingår i: Journal of Computer Science and Technology. - : SPRINGER SINGAPORE PTE LTD. - 1000-9000 .- 1860-4749. ; 38:2, s. 405-421
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Tidskriftsartikel (refereegranskat)abstract
- Online testing is critical to ensuring reliable operations of the next generation of supercomputers based on a kilo-core network-on-chip (NoC) interconnection fabric. We present a parallel software-based self-testing (SBST) solution that makes use of the bounded model checking (BMC) technique to generate test sequences and parallel packets. In this method, the parallel SBST with BMC derives the leading sequence for each routers internal function and detects all functionally- testable faults related to the function. A Monte-Carlo simulation algorithm is then used to search for the approximately optimum configuration of the parallel packets, which guarantees the test quality and minimizes the test cost. Finally, a multi-threading technology is used to ensure that the Monte-Carlo simulation can reach the approximately optimum configuration in a large random space and reduce the generating time of the parallel test. Experimental results show that the proposed method achieves a high fault coverage with a reduced test overhead. Moreover, by performing online testing in the functional mode with SBST, it effectively avoids the over-testing problem caused by functionally untestable turns in kilo-core NoCs.
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| 2. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation
- 2011
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Ingår i: <em>Digital System Design (DSD), 2011 14th Euromicro Conference on</em>. - : IEEE. - 9781457710483 ; , s. 197-204
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Konferensbidrag (refereegranskat)abstract
- High temperature and process variation areundesirable effects for modern systems-on-chip. The hightemperature is a prominent issue during test and should be takencare of during the test process. Modern SoCs, affected by largeprocess variation, experience rapid and large temperaturedeviations and, therefore, a traditional static test schedule which isunaware of these deviations will be suboptimal in terms of speedand/or thermal-safety. This paper presents an adaptive testscheduling method which addresses the temperature deviationsand acts accordingly in order to improve the test speed andthermal-safety. The proposed method is divided into acomputationally intense offline-phase, and a very simple online-phase.In the offline-phase a schedule tree is constructed, and inthe online-phase the appropriate path in the schedule tree istraversed, step by step and based on temperature sensor readings.Experiments have demonstrated the efficiency of the proposedmethod.
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| 3. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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An Efficient Temperature-Gradient Based Burn-In Technique for 3D Stacked ICs
- 2014
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Ingår i: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. - : IEEE conference proceedings. - 9783981537024
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Konferensbidrag (refereegranskat)abstract
- Burn-in is usually carried out with high temperature and elevated voltage. Since some of the early-life failures depend not only on high temperature but also on temperature gradients, simply raising up the temperature of an IC is not sufficient to detect them. This is especially true for 3D stacked ICs, since they have usually very large temperature gradients. The efficient detection of these early-life failures requires that specific temperature gradients are enforced as a part of the burn-in process. This paper presents an efficient method to do so by applying high power stimuli to the cores of the IC under burn-in through the test access mechanism. Therefore, no external heating equipment is required. The scheduling of the heating and cooling intervals to achieve the required temperature gradients is based on thermal simulations and is guided by functions derived from a set of thermal equations. Experimental results demonstrate the efficiency of the proposed method.
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| 4. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs
- 2015
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Ingår i: <em>20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, Jan. 19-22, 2015.</em>. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781479977925 ; , s. 526-531
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Konferensbidrag (refereegranskat)abstract
- In a modern 3D IC, electrical connections between vertically stacked dies are made using through silicon vias. Through silicon vias are subject to undesirable early-life effects such as protrusion as well as void formation and growth. These effects result in opens, resistive opens, and stress induced carrier mobility reduction, and consequently circuit failures. Operating the ICs under extreme temperature cycling can effectively accelerate such early-life failures and make them detectable at the manufacturing test process. An integrated temperature-cycling acceleration and test technique is introduced in this paper that integrates a temperature-cycling acceleration procedure with pre-, mid-, and post-bond tests for 3D ICs. Moreover, it reduces the need for costly temperature chamber based temperature-cycling acceleration procedures. All these result in a reduction in the overall test costs. The proposed method is a schedule-based solution that creates the required temperature cycling effect along with performing the tests. Experimental results demonstrate its efficiency.
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| 5. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Efficient Test Application for Rapid Multi-Temperature Testing
- 2015
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Ingår i: Proceedings of the 25th edition on Great Lakes Symposium on VLSI. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450334747 ; , s. 3-8
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Different defects may manifest themselves at different temperatures. Therefore, the tests that target such temperature-dependent defects must be applied at different temperatures appropriate for detecting them. Such multi-temperature testing scheme applies tests at different required temperatures. It is known that a test's power dissipation depends on the previously applied test. Therefore, the same set of tests when organized differently dissipates different amounts of power. The technique proposed in this paper organizes the tests efficiently so that the resulted power levels lead to the required temperatures. Consequently a rapid multi-temperature testing is achieved. Experimental studies demonstrate the efficiency of the proposed technique.
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| 6. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Heuristics for Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation
- 2011
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Ingår i: <em>The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011</em>.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- High working temperature and process variation are undesirable effects for modern systems-on-chip. The high temperature should be taken care of during the test. On the other hand, large process variations induce rapid and large temperature deviations causing the traditional static test schedules to be suboptimal in terms of speed and/or thermal-safety. A remedy to this problem is an adaptive test schedule which addresses the temperature deviations by reacting to them. Our adaptive method is divided into a computationally intense offline-phase, and a very simple online-phase. In this paper, heuristics are proposed for the offline phase in which the optimized schedule tree is found. In the online-phase, based on the temperature sensor readings the appropriate path in the schedule tree is traversed. Experiments are made to tune the proposed heuristics and to demonstrate their efficiency.
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| 7. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Process-variation and Temperature Aware SoC Test Scheduling Technique
- 2013
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Ingår i: Journal of electronic testing. - : Springer. - 0923-8174 .- 1573-0727. ; 29:4, s. 499-520
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Tidskriftsartikel (refereegranskat)abstract
- High temperature and process variation are undesirable phenomena affecting modern Systems-on-Chip (SoC). High temperature is a well-known issue, in particular during test, and should be taken care of in the test process. Modern SoCs are affected by large process variation and therefore experience large and time-variant temperature deviations. A traditional test schedule which ignores these deviations will be suboptimal in terms of speed or thermal-safety. This paper presents an adaptive test scheduling method which acts in response to the temperature deviations in order to improve the test speed and thermal safety. The method consists of an offline phase and an online phase. In the offline phase a schedule tree is constructed and in the online phase the appropriate path in the schedule tree is traversed based on temperature sensor readings. The proposed technique is designed to keep the online phase very simple by shifting the complexity into the offline phase. In order to efficiently produce high-quality schedules, an optimization heuristic which utilizes a dedicated thermal simulation is developed. Experiments are performed on a number of SoCs including the ITC'02 benchmarks and the experimental results demonstrate that the proposed technique significantly improves the cost of the test in comparison with the best existing test scheduling method.
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| 8. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Process-Variation and Temperature Aware SoC Test Scheduling Using Particle Swarm Optimization
- 2011
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Ingår i: <em>The 6th IEEE International Design and Test Workshop (IDT'11), Beirut, Lebanon, December 11–14, 2011.</em>. - : IEEE. - 9781467304689 - 9781467304672
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Konferensbidrag (refereegranskat)abstract
- High working temperature and process variation are undesirable effects for modern systems-on-chip. It is well recognized that the high temperature should be taken care of during the test process. Since large process variations induce rapid and large temperature deviations, traditional static test schedules are suboptimal in terms of speed and/or thermalsafety. A solution to this problem is to use an adaptive test schedule which addresses the temperature deviations by reacting to them. We propose an adaptive method that consists of a computationally intense offline-phase and a very simple onlinephase. In the offline-phase, a near optimal schedule tree is constructed and in the online-phase, based on the temperature sensor readings, an appropriate path in the schedule tree is traversed. In this paper, particle swarm optimization is introduced into the offline-phase and the implications are studied. Experimental results demonstrate the advantage of the proposed method.
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| 9. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Process-Variation Aware Multi-temperature Test Scheduling
- 2014
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Ingår i: 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems. - : IEEE conference proceedings. ; , s. 32-37
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Konferensbidrag (refereegranskat)abstract
- Chips manufactured with deep sub micron technologies are prone to large process variation and temperature-dependent defects. In order to provide high test efficiency, the tests for temperature-dependent defects should be applied at appropriate temperature ranges. Existing static scheduling techniques achieve these specified temperatures by scheduling the tests, specially developed heating sequences, and cooling intervals together. Because of the temperature uncertainty induced by process variation, a static test schedule is not capable of applying the tests at intended temperatures in an efficient manner. As a result the test cost will be very high. In this paper, an adaptive test scheduling method is introduced that utilizes on-chip temperature sensors in order to adapt the test schedule to the actual temperatures. The proposed method generates a low cost schedule tree based on the variation statistics and thermal simulations in the design phase. During the test, a chip selects an appropriate schedule dynamically based on temperature sensor readings. A 23% decrease in the likelihood that tests are not applied at the intended temperatures is observed in the experimental studies in addition to 20% reduction in test application time.
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| 10. |
- Aghaee Ghaleshahi, Nima, et al.
(författare)
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Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation
- 2010
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Ingår i: <em>19th IEEE Asian Test Symposium (ATS10), Shanghai, China, December 1-4, 2010.</em>. - 9781424488414
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Konferensbidrag (refereegranskat)abstract
- Systems on Chip implemented with deep submicron technologies suffer from two undesirable effects, high power density, thus high temperature, and high process variation, which must be addressed in the test process. This paper presents two temperature-aware scheduling approaches to maximize the test throughput in the presence of inter-chip process variation. The first approach, an off-line technique, improves the test throughput by extending the traditional scheduling method. The second approach, a hybrid one, improves further the test throughput with a chip classification scheme at test time based on the reading of a temperature sensor. Experimental results have demonstrated the efficiency of the proposed methods.
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