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- Pinardi, Kuntjoro, 1968, et al.
(författare)
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Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test
- 2004
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 48:7, s. 1119-1126
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Tidskriftsartikel (refereegranskat)abstract
- Electrothermal effects during the unclamped inductive switching (UIS) of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors have been studied by device simulation. In the UIS test all the energy stored in the inductor during the on state is dumped directly into the device when the device is turned off. This extreme condition during the UIS test will give ratings for the power device and gives a measure for the stability of the device in the breakdown regime. Electrothermal simulations of this device are evaluated under boundary conditions imposed by the UIS circuit. Simulations show that UIS involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behaviour. The experiments at ambient temperature of 100 °C show that the breakdown voltage decreases as the drain voltage increases. This indicates that the parasitic BJT has been turned on and causes an open-base bipolar transistor breakdown voltage. © 2004 Elsevier Ltd. All rights reserved.
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- Pinardi, Kuntjoro, 1968, et al.
(författare)
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High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling
- 2004
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Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 51:5, s. 790-796
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Tidskriftsartikel (refereegranskat)abstract
- Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100°C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.
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- Pinardi, Kuntjoro, 1968
(författare)
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Modelling of High Power SOI Vertical DMOS Transistors and Flip-chip Packages
- 2003
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Part I: Vertical DMOS Transistors System level integration is a major trend in the electronic industry at the moment. For automotive applications in particular it is desirable to integrate CMOS logic circuits and different types of power devices. One of the methods to separate these devices from each other is by having a Silicon-on-Insulator (SOI) material providing dielectric isolation between high and low voltage parts. An important question is related to the performance of these dielectrically isolated devices. High power vertical DMOS transistors (VDMOSFETs) on SOI are demonstrated with a CMOS compatible fabrication process. A large number of defects are created in the structure if the trench formation is performed prior to the device fabrication. The defect generation has been reduced signicantly by moving the trench formation towards the end of fabrication steps. In this way the trenches are not exposed to high temperatures. Our measurements of the fabricated SOI VDMOSFETs in the static region are in good agreement with the expected impact of the self-heating simulations on the saturation behaviour. Looking into details the carrier dynamics during the Unclamped Inductive Switching test can easily reveal the potential of having the parasitic bipolar transistors turned on. Furthermore high-temperature measurements point out that the parasitic BJT effect is activated. Switching simulations show that the substrate and oxide capacitors provide a second path for the current to flow during the discharging of the inductor. It can happen that the maximum current through the SOI device is separated in time from the maximum voltage across the device, thereby reducing the maximum power. Part II: Finite Element Calculations of Flip-chip Joints Flip-chip joining using anisotropically conductive adhesive (ACA) has become a very attractive technique for electronics packaging. In this work, the strain development during the thermal cycling test of ip-chip joining with different bump heights was studied. The effect of bump height is signicant in the interface between the bumps and the pads. Our calculations show that there is practically no effect of the bump height on the strain variation in the bumps and in the pads.
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