| 1. |
- Ahsan, Naveed, et al.
(författare)
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A 1.1V 6.2mW, Highly Linear Wideband RF Front-end for Multi-Standard Receivers in 90nm CMOS
- 2012
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Ingår i: Analog Integrated Circuits and Signal Processing. - : SpringerLink. - 0925-1030 .- 1573-1979. ; 70:1, s. 79-90
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the design and implementation of a low power, highly linear, wideband RF front-end in 90nm CMOS. The architecture consists of an inverter-like common gate low noise amplifier followed by a passive ring mixer. The proposed architecture achieves high linearity in a wide band (0.5-6GHz) at very low power. Therefore, it is a suitable choice for software defined radio (SDR) receivers. The chip measurement results indicate that the inverter-like common gate input stage has a broadband input match achieving S11 below -8.8dB up to 6GHz. The measured single sideband noise figure at an LO frequency of 2GHz and an IF of 10MHz is 6.25dB. The front-end achieves a voltage conversion gain of 4.5dB at 1GHz with 3dB bandwidth of more than 6GHz. The measured input referred 1dB compression point is +1.5dBm while the IIP3 is +11.73dBm and the IIP2 is +26.23dBm respectively at an LO frequency of 2GHz. The RF front-end consumes 6.2mW from a 1.1V supply with an active chip area of 0.0856mm2.
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| 5. |
- Andersson, Stefan, et al.
(författare)
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Multiband Direct RF-Sampling Receiver Front-End for WLAN in 0.13 μm CMOS
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- In this paper a flexible RF-sampling front-end primarily intended for WLAN operating in the 2.4 GHz and 5- 6 GHz bands is presented. The circuit is implemented in a 0.13 mum CMOS process with certain built-in test features. It consists of a wideband LNA and a SC discrete-time decimation filter used as a sampling IQ down-converter. The architecture is generic and scalable in frequency and it can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz. The decimation factor is 8 or 16 rendering the following A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. At the power consumption of 176 mW the circuit achieves specs that are satisfactory for WLAN applications.
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| 6. |
- Arshad, Sana, et al.
(författare)
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50-830 MHz noise and distortion canceling CMOS low noise amplifier
- 2018
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 60, s. 63-73
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a modified resistive shunt feedback topology is proposed that performs noise cancelation and serves as an opposite polarity non-linearity generator to cancel the distortion produced by the main stage. The proposed topology has a bandwidth similar to a resistive shunt feedback LNA, but with a superior noise figure (NF) and linearity. The proposed wideband LNA is fabricated in 130 nm CMOS technology and occupies an area of 0.5 mm(2). Measured results depict 3-dB bandwidth from 50 to 830 MHz. The measured gain and NF at 420 MHz are 17 dB and 2.2 dB, respectively. The high value of the 1/f noise is one of the key problems in low frequency CMOS designs. The proposed topology also addresses this challenge and a low NF is attained at low frequencies. Measured 811 and S22 are better than -8.9 dB and -8.5 dB, respectively within the 0.05-1 GHz band. The 1-dB compression point is -11.5 dBm at 700 MHz, while the IIP3 is -6.3 dBm. The forward core consumes 14 mW from a 1.8 V supply. This LNA is suitable for VHF and UHF SDR communication receivers.
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| 7. |
- Arshad, Sana, et al.
(författare)
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Highly Linear Inductively Degenerated 0.13 mu m CMOS LNA using FDC Technique
- 2014
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Ingår i: 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS). - : IEEE. - 9781479952304 ; , s. 225-228
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Konferensbidrag (refereegranskat)abstract
- In this paper, a highly linear, inductively degenerated, common source narrowband LNA is presented. An extremely simple feed-forward distortion circuit (FDC) which consists of an appropriately sized ac-coupled diode connected NMOS is proposed. This circuit generates distortion components at output, when added at the input node as a feed forward element (M-6). These distortion components partially cancel the 3rd order nonlinearity of the cascode pair (M-2 and M-3), thus improving the overall linearity of LNA. The prototype is manufactured in standard 0.13 mu m CMOS process from IBM. Simulation and partial measurement results show the S11 and S22 to be -19.27dB and -7.14dB respectively at 2.45GHz. The simulation results of the LNA demonstrate a power gain of 18.5dB, NF of 4.38dB, input referred 1dBCP of -11.76dBm and IIP3 of +0.7dBm consuming 27.7mA from 1.0V power supply. The proposed LNA achieves the best input referred IIP3 reported in recent literature using 0.13 mu m CMOS in 2.4GHz frequency band.
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| 8. |
- Dabrowski, Jerzy, et al.
(författare)
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Boosting SER Test for RF Transceivers by Simple DSP Technique
- 2007
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Ingår i: DATE '07 Design, Automation & Test in Europe Conference & Exhibition, 2007.. - : IEEE. - 9783981080124 ; , s. 1-6
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Konferensbidrag (refereegranskat)abstract
- The paper presents a new technique of symbol error rate test (SER) for RF transceivers. A simple DSP algorithm implemented at the receiver baseband is introduced in terms of constellation correction, which is usually used to compensate for IQ imbalance. The test is oriented at detection of impairments in gain and noise figure in a transceiver frontend. The proposed approach is shown to enhance the sensitivity of a traditional SER test to the limits of its counterpart, the error vector magnitude (EVM) test. Its advantage over EVM is in simple implementation, lower DSP overhead and the ability of achieving a larger dynamic range of the test response. Also the test time is saved compared to a traditional SER test. The technique is validated by a simulation model of a Wi-Fi transceiver implemented in MatlabTM.
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| 9. |
- Dabrowski, Jerzy, et al.
(författare)
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Built-in Loopback Test for IC RF Transceivers
- 2010
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - 1063-8210 .- 1557-9999. ; 18:6, s. 933-946
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Tidskriftsartikel (refereegranskat)abstract
- The essentials of the on-chip loopback test for integrated RF transceivers are presented. The available on-chip baseband processor serves as a tester while the RF front-end is under test enabled by on-chip test attenuator and in some cases by an offset mixer, too. Various system-level tests, like BER, EVM or spectral measurements are discussed. By using this technique in mass production, the RF test equipment can be largely avoided and the test cost reduced. Different variants of the loopback setup including the bypassing technique and RF detectors to boost the chip testability are considered. The existing limitations and tradeoffs are discussed in terms of test feasibility, controllability, and observability versus the chip performance. The fault-oriented approach supported by sensitization technique is put in contrast to the functional test. Also the impact of production tolerances is addressed in terms of a simple statistical model and the detectability thresholds. The paper is based on the present and previous work of the authors, largely revised and upgraded to provide a comprehensive description of the on-chip loopback test. Simulation examples of practical communication transceivers such as WLAN and EDGE under test are also included.
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| 10. |
- Dabrowski, Jerzy, 1952-, et al.
(författare)
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Offset Loopback Test For IC RF Transceivers
- 2006
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Ingår i: Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.. - Lodz, Poland : Dpt of Microelectronics and Computer Science, Technical University of Lodz. - 8392263227 ; , s. 583-586
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Konferensbidrag (refereegranskat)abstract
- In this paper we develop an offset loopback test setup for integrated RF transceivers (TRx's). Basically, addressed are architectures, which are not suitable for direct loopback test such as FDD transceivers or TDD transceivers where the transmitter (Tx) and receiver (Rx) share one frequency synthesizer (called VCO modulating TRx's). The technique makes use of an extra mixer put on chip to compensate for the incompatibility of the Tx and Rx, i.e. to compensate for a difference between the transmit- and the receive frequency, and/or to introduce a baseband signal needed for test. We discuss the problem in terms of system-level models, which are implemented and verified in Matlabtrade
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