| 1. |
- Mikhaylov, Aleksey I., et al.
(författare)
-
On the ion implantation of phosphorus as a method for the passivation of states at the interface between 4H-SiC and SiO2 produced by thermal oxidation in dry oxygen
- 2014
-
Ingår i: Semiconductors (Woodbury, N.Y.). - : Maik Nauka-Interperiodica Publishing. - 1063-7826 .- 1090-6479. ; 48:12, s. 1581-1585
-
Tidskriftsartikel (refereegranskat)abstract
- A method is suggested for reducing the density of surface states at the 4H-SiC/SiO2 interface by the implantation of phosphorus ions into a 4H-SiC epitaxial layer immediately before the growth of a gate insulator in an atmosphere of dry oxygen. A significant decrease in the density of surface states is observed at a phosphor-ion concentration at the SiO2/SiC interface exceeding 1018 cm−3. However, together with the passivation of surface states, the introduction of phosphorus ions leads to an increase in the built-in charge in the insulator and also slightly deteriorates the reliability of the gate insulator fabricated by this technique.
|
|
| 2. |
- Bakowski, Mietek, et al.
(författare)
-
Design and characterization of newly developed 10 kV 2 A SiC p-i-n diode for soft-switching industrial power supply
- 2015
-
Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers Inc.. - 0018-9383 .- 1557-9646. ; 62:2, s. 366-373
-
Tidskriftsartikel (refereegranskat)abstract
- 10 kV, 2 A SiC p-i-n diodes have been designed and fabricated. The devices feature excellent stability of forward characteristics and robust junction termination with avalanche capability of 1 J. The fabricated diodes have been electrically evaluated with respect to dynamic ON-state voltage, reverse recovery behavior, bipolar stability, and avalanche capability. More than 60% reduction of losses has been demonstrated using newly developed 10-kV p-i-n diodes in a multikilowatt high voltage, high-frequency dc/dc soft-switching converter
|
|
| 3. |
- Ghandi, Reza, et al.
(författare)
-
Surface-passivation effects on the performance of 4H-SiC BJTs
- 2011
-
Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 58, s. 259-265
-
Tidskriftsartikel (refereegranskat)abstract
- In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.
|
|
| 4. |
- Hertel, Stefan, et al.
(författare)
-
Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics
- 2012
-
Ingår i: Nature Communications. - : Springer Science and Business Media LLC. - 2041-1723. ; 3
-
Tidskriftsartikel (refereegranskat)abstract
- Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10 4 and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.
|
|
| 5. |
- Lorenzzi, Jean, et al.
(författare)
-
3C-SiC MOS based devices : from material growth to device characterization
- 2011
-
Ingår i: Silicon carbide and related materials 2010. - : Trans Tech Publications, Ltd.. ; , s. 433-
-
Konferensbidrag (refereegranskat)abstract
- In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (D-it)can be drastically decreased down to 1.2 x 10(10) eV(-1)cm(-2) at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.
|
|
| 6. |
- Mikhaylov, Aleksey I., et al.
(författare)
-
Alternative method of interface traps passivation by introducing of thin silicon nitride layer at 4H-SiC/SiO2 interface
- 2014
-
Ingår i: Materials Research Society Symposium Proceedings. - : Springer Science and Business Media LLC.
-
Konferensbidrag (refereegranskat)abstract
- An alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).
|
|
| 7. |
- Mikhaylov, Aleksey I., et al.
(författare)
-
Effect of phosphorus implantation prior to oxidation on electrical properties of thermally grown SiO2/4H-SiC MOS structures
- 2015
-
Ingår i: Mater. Sci. Forum. - : Trans Tech Publications Ltd. - 9783038352945 ; , s. 133-138
-
Konferensbidrag (refereegranskat)abstract
- The electrical properties of metal-oxide-semiconductor (MOS) devices fabricated using dry oxidation on phosphorus-implanted n-type 4H-SiC (0001) epilayers have been investigated. MOS structures were compared in terms of interface traps and reliability with reference sample which was produced by dry oxidation under the same conditions. The notably lower interface traps density measured in MOS capacitor with phosphorus concentration exceeding 1018 cm-3 at the SiO2/SiC interface was attributed to interface traps passivation by incorporated phosphorus ions. © (2015) Trans Tech Publications, Switzerland.
|
|
| 8. |
- Roensch, Sebastian, et al.
(författare)
-
Drain-current deep level transient spectroscopy investigation on epitaxial graphene/6H-SiC field effect transistors
- 2014
-
Ingår i: Mater. Sci. Forum. - 9783038350101 ; , s. 436-439
-
Konferensbidrag (refereegranskat)abstract
- The electrically active deep levels in a graphene/silicon carbide field effect transistor (FET) were investigated by drain-current deep level transient spectroscopy (ID-DLTS). An evaluation procedure for ID-DLTS is developed in order to obtain the activation energy, the capture cross section and the trap concentration. We observed three defect centers corresponding to the intrinsic defects E1/E2, Ei and Z1/Z2 in n-type 6H-SiC. The determined parameters have been verified by conventional capacitance DLTS.
|
|
| 9. |
- Schöner, Adolf, et al.
(författare)
-
Progress in buried grid technology for improvements in on-resistance of high voltage SiC devices
- 2016
-
Ingår i: ECS Transactions. - : The Electrochemical Society. - 9781607685395 ; , s. 183-190
-
Konferensbidrag (refereegranskat)abstract
- Buried grid technology is suggested to protect field sensitive device areas from high electric field in order to improve the high temperature and high voltage performance of SiC devices. More than three orders of magnitude lower leakage currents have been demonstrated at high temperature operation. The drawback is that the total resistance increases due to the introduction of the buried grid leading to higher voltage drop at rated current and higher conduction losses. In this paper, we discuss doping and barrier engineering methods in order to take full advantage of the superior shielding effect of the buried grid technology and at the same time minimize the effect on the current conduction. As example, the design considerations for a 1200 V SiC buried grid JBS diode in terms of epi structure doping as well as buried grid properties is comprehensively investigated to optimize the on-state condition.
|
|
| 10. |
- Sledziewski, Tomasz, et al.
(författare)
-
Reduction of density of 4H-SiC/SiO2 interface traps by pre-oxidation phosphorus implantation
- 2014
-
Ingår i: Materials Science Forum. - 9783038350101 ; , s. 575-578
-
Konferensbidrag (refereegranskat)abstract
- The effect of phosphorus (P) on the electrical properties of the 4H-SiC/SiO2 interface was investigated. Phosphorus was introduced by surface-near ion implantation with varying ion energy and dose prior to thermal oxidation. Secondary ion mass spectrometry revealed that only part of the implanted P followed the oxidation front to the interface. A negative flatband shift due to residual P in the oxide was found from C-V measurements. Conductance method measurements revealed a significant reduction of density of interface traps Dit with energy EC-Eit > 0.3 V for P+-implanted samples with [P]interface = 1.5 · 1018 cm-3 in the SiC layer at the interface. .
|
|
