| 1. |
- Albertsson, Dagur Ingi
(författare)
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Spintronic and Electronic Oscillators for Magnetic Field Sensing and Ising Machines
- 2023
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Oscillators can exhibit a range of complex dynamics which are often encountered in nature. These characteristics include synchronization, injection locking, chaos, bifurcations, etc. To date, the applications of electronic oscillators has mostly been limited to communication systems. However, in recent years, the possibility of using the rich dynamics of oscillators in unconventional applications, including time-based information processing and computational applications, has been also explored. In this thesis, this potential is investigated using emerging spintronic oscillators and established electronic oscillators. The first part of this thesis targets emerging spintronic oscillators, which exhibit a range of attractive features, including GHz operating frequency, wide tunability and nanoscale size. To explore the potential of these devices, an electrical behavioural model was developed for the promising three-terminal spin-Hall nano-oscillator. The behavioural model is based on the macrospin approximation, which is commonly used to describe the operation principles of spintronic oscillators, and it was implemented in Verilog-A. Moreover, the behavioural model was verified against experimental measurements from literature, demonstrating that the most important characteristics of three-terminal spin-Hall nano-oscillators are accurately captured. Subsequently, two potential applications that could benefit from the unique characteristics of spintronic oscillators were identified and explored. First, a magnetic field sensing system, which takes advantage of the wide frequency tunability of spintronic oscillators as a function of externally applied magnetic field, was proposed and demonstrated. This sensing system, inspired by voltage-controlled oscillator analog-to-digital converters, shows performance similar to the state-of-the-art magnetic field sensors, making it a promising application for spintronic oscillators. Next, the possibility of utilizing spintronic oscillators to realize Ising machines (IMs) was explored and demonstrated with numerical simulations. This was the first-time demonstration of spintronic oscillator-based Ising machines. The numerical simulation results show that spintronic oscillators are a promising device to realize ultra-fast Ising Machines able to solve complex combinatorial optimization problems on nano-second time scale.The second part of the thesis extends on the idea of oscillator-based IMs, but using electronic oscillators. The potential of realizing highly reconfigurable oscillator-based IMs based on quasiperiodically modulated coupling was explored. The advantages and potential challenges associated with this approach were highlighted, and a proof-of-concept IM using CMOS ring oscillators was proposed and simulated. Finally, a completely new type of IMs based on bifurcations in a network of coupled Duffing oscillators was proposed and developed. This work highlights a new research direction based on using dynamical systems implemented with analog circuits to realize IMs.
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| 2. |
- Chaourani, Panagiotis, 1989-
(författare)
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Sequential 3D Integration - Design Methodologies and Circuit Techniques
- 2019
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.
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| 3. |
- Fernández Schrunder, Alejandro David, 1993-
(författare)
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Fully Integrated Bioimpedance Spectroscopy Interface for Wearable Electrical Impedance Myography
- 2024
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Multi-Frequency surface Electrical Impedance Myography (MF-sEIM) is a technique that provides valuable electrophysiological information of muscles. This technique measures bio-Z spectroscopy of muscles, and applies Ohm's law by injecting a small-amplitude and high-frequency current into tissues and measuring the voltage response. As biological tissues are electrolytic conductors, this technique provides information on fundamental dielectric properties of tissues, which are an objective biomarker of neuromuscular disorders and have practical value in several muscle healthcare applications. Due to its versatility, simplicity, and ease of integration, this technique is a great candidate to complement stand-alone surface electromyography (sEMG) in wearable devices for continuous monitoring of muscle health. Nonetheless, wearable MF-sEIM imposes challenging requirements on the bio-Z spectroscopy interface. Previously reported solutions fall short of meeting these requirements, or do so with low power efficiency.This thesis focuses on the research and development of a fully integrated bio-Z spectroscopy interface, which complies with the challenging requirements of wearable MF-sEIM in a power-efficient way. The electrophysiological mechanisms of MF-sEIM and the system-level requirements for clinical relevance were investigated, as MF-sEIM is a relatively novel technique, which requires standarization. From this established set of requirements, the main building blocks of the \mbox{bio-Z} spectroscopy interface, i.e., the current signal generator (CSG), and voltage readout, were developed. The CSG generates pseudo-sine waves through direct digital synthesis (DDS) to obtain the required linearity with high power efficiency. A high-linearity full current-mode CSG was also proposed to comply with the stricter bio-Z accuracy requirements of clinical diagnostics. The voltage readout is based on a low-IF quadrature (I/Q) demodulation architecture and features a pseudo 2-path bandpass (BP) Delta-Sigma ADC to achieve high precision and power-to-noise efficiency. A mixer-first analog front-end (AFE) was also proposed to enable bio-Z spectroscopy measurements employing dry electrodes. The bio-Z interface was integrated with a 16-Channel sEMG AFE and a 4-Channel neuromuscular stimulator (NMES) in an application-specific integrated circuit (ASIC). Experimental results show that the implemented bio-Z spectroscopy interface achieves a comparable performance with the state of the art, while being capable of detecting the large baseline and the time-varying impedances of muscle. A proof-of-concept system, based on the multi-modal ASIC, was developed. This system demonstrates the potential of combining real-time monitoring of MF-sEIM and sEMG for detecting muscle fatigue, enabling efficient closed-loop NMES.
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| 4. |
- Kargarrazi, Saleh, 1985-
(författare)
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High Temperature Bipolar SiC Power Integrated Circuits
- 2017
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In the recent decade, integrated electronics in wide bandgap semiconductor technologies such as Gallium Nitride (GaN) and Silicon Carbide (SiC) have been shown to be viable candidates in extreme environments (e.g high-temperature and high radiation). Such electronics have applications in down-hole drilling, automobile-, air- and space- industries. In this thesis, integrated circuits (ICs) in bipolar 4H-SiC for high-temperature power applications are explored. In particular, device modelling, circuit design, layout design, and measurements are discussed for a range of circuits including operational amplifiers, linear voltage regulators, drivers for power switches, and power converters with integrated control. The circuits were demonstrated and tested from 25 °C up to 500 °C. Circuit design in bipolar SiC technology involves challenges such as the fabrication process’ uncertainties and incomplete models of the devices. Furthermore, high temperature modelling of the integrated devices is needed for circuit design and simulation. From the circuit design viewpoint, techniques such as negative-feedback, temperature-insensitive biasing, buffering and Darlington stages, and amplifiers with fewer gain stages, were shown to be useful for high-temperature IC design in bipolar SiC. It is shown that the linear voltage regulator can be improved by using a tailored high-current lateral Darlington power device in the same fabrication process. This results in a high temperature high current power supply solution. Moreover, the drivers can be improved by design in order to provide higher voltage levels and peak currents for the power devices (bipolar and MOSFET based). In addition, a DC-DC converter with fully integrated hysteretic control is designed taking advantage of several sub-circuits such as operational amplifier, Schmitt trigger and driver for the power switch. This study is followed by preliminary experimental results for the converter and controller IC.
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| 5. |
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| 6. |
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| 7. |
- Chen, Kairang, 1986-
(författare)
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Energy-Efficient Data Converters for Low-Power Sensors
- 2016
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energy-harvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxide-semiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications.The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-μm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage capacitive charge pump (CCP) is utilized to achieve the gain-stage instead of using the switch capacitor (SC) amplifier. Unity-gain OTAs have been used as the analog buffers to prevent the charge sharing between the CCP stages. The detailed design considerations are given in this work. The prototype ADC, designed and fabricated in a low-cost 0.35-μm CMOS process, achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 μW and 96 μW, respectively. The corresponding Schreier FoM are 166.7 dB and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR > 75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.As the low-power sensors might be active only for very short time triggered by an external pulse to acquire the data, the third work is a 14-bit asynchronous two-stage pipelined SAR ADC which has been designed and simulated in 0.18-μm CMOS process. A self-synchronous loop based on an edge detector is utilized to generate an internal clock with variable phase. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Three separate asynchronous clock generators are implemented to create the control signals for two sub-ADCs and the gain-stage between. Aiming to reduce the power consumption of the gain-stage, simple source followers as the analog buffers are implemented in the 3-stage CCP gain-stage. Post-layout simulation results show that the ADC achieves a SNDR of 83.5 dB while consuming 2.39 μW with a sampling rate of 10 kS/s. The corresponding Schreier FoM is 176.7 dB.
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| 8. |
- Chen, Tingsu
(författare)
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CMOS High Frequency Circuits for Spin Torque Oscillator Technology
- 2014
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively.First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL.The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given.
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| 9. |
- Chen, Tingsu
(författare)
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Spin Torque Oscillator Modeling, CMOS Design and STO-CMOS Integration
- 2015
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration.An electrical model, which can capture magnetic tunnel junction (MTJ) STO's characteristics, while enabling system- and circuit-level designs and performance evaluations, is of great importance for the development of MTJ STO-based applications. A comprehensive and compact analytical model, which is based on macrospin approximations and can fulfill the aforementioned requirements, is proposed. This model is fully implemented in Verilog-A, and can be used for efficient simulations of various MTJ STOs. Moreover, an accurate phase noise generation approach, which ensures a reliable model, is proposed and successfully used in the Verilog-A model implementation. The model is experimentally validated by three different MTJ STOs under different bias conditions.CMOS circuits, which can enhance the limited output power of MTJ STOs to levels that are required in different applications, are proposed, implemented and tested. A novel balun-low noise amplifier (LNA), which can offer sufficient gain, bandwidth and linearity for MTJ STO-based magnetic field sensing applications, is proposed. Additionally, a wideband amplifier, which can be connected to an MTJ STO to form a highly-tunable microwave oscillator in a phase-locked loop (PLL), is also proposed. The measurement results demonstrate that the proposed circuits can be used to develop MTJ STO-based magnetic field sensing and microwave source applications.The investigation of possible STO-CMOS IC integration approaches demonstrates that the wire-bonding-based integration is the most suitable approach. Therefore, a giant magnetoresistance (GMR) STO is integrated with its dedicated CMOS IC, which provides the necessary functions, using the wire-bonding-based approach. The RF characterization of the integrated GMR STO-CMOS IC system under different magnetic fields and DC currents shows that such an integration can eliminate wave reflections. These findings open the possibility of using GMR STOs in magnetic field sensing and microwave source applications.
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| 10. |
- Garcia, Julian, 1977-
(författare)
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Digitally Enhanced Continuous-Time Sigma-Delta Analogue-to-Digital Converters
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The continuous downscaling of CMOS technology presents advantagesand difficulties for IC design. While it allows faster, denser and more energy efficient digital circuits, it also imposes several challenges which limit the performance of analogue circuits. Concurrently, applications are continuously pushing the boundaries of power efficiency and throughput of electronic systems. Accordingly, IC design is increasingly shifting into highly digital systems with few necessary analogue components. Particularly, continuous-time (CT) sigma-delta (ΣΔ) analogue-to-digital converters (ADCs) have recently received a growing interest, covering high-resolution medium-speed requirementsor offering low power alternatives to low speed applications. However, there are still several aspects that deserve further investigation so as to enhancethe ADC’s performance and functionality. The objective of the research performed in this thesis is the investigation of digital enhancement solutions for CT ΣΔ ADCs. In particular, two aspects are considered in this work. First, highly digital techniques are investigated to minimize circuit impairments, with the objective of providing solutions with reduced analogue content. In this regard, a multi-bit CT ΣΔ modulator with reduced number of feedback levels is explored to minimize the use of linearisation techniques in the DAC. The proposed architecture is designed and validated through behavioural simulations targeting a mobile application. Additionally, a novel self-calibration technique, using test-signal injection and digital cancellation, is proposed to counteract process variations affecting single loop CT implementations. The effectiveness of the calibration technique is confirmed through corner simulations using behavioural models and shows that stability issues are minimized and that a 7 dB SNDR degradation can be avoided. The second aspect of this thesis investigates the use of high order CT modulators in incremental ΣΔ (IΣΔ) and extended-range IΣΔ ADCs, with the objective of offering low-power alternatives for low-speed high-resolution multi-channel applications. First, a 3rd order single loop CT IΣΔ ADC, targeting an 8-channel 500 Ksamples/sec rate per channel recording system for neuropotential sensors, is proposed, fabricated and tested. The proposed architecture lays the theoretical groundwork and demonstrates a competitive performance of high-order CT IΣΔ ADCs for low-power multi-channel applications. The ADC achieves 65.3 dB/64 dB SNR/SNDR and 68.2 dB dynamic range. The modulator consumes 96 μW from a 1.6 V power supply. Additionally, the use of extended range approach in CT IΣΔ ADCs is investigated,so as to reduce the required number of cycles per conversion while benefiting from the advantages of a CT implementation. The operation, influence of filter topology and impact of circuit non-idealities are first analysed using a general approach and later validated through a test-case. It was found that, by applying analogue-digital compensation in the digital domain, it is possible to minimize the noise leakage due to analogue-digital transfer function mismatches and benefit from relaxed amplifiers’ finite gain-bandwidth product and finite DC gain, allowing, as a consequence, a power conscious alternative.
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