| 1. |
- Jalili, Armin, et al.
(författare)
-
A nonlinearity error calibration technique for pipelined ADCs
- 2011
-
Ingår i: Integration. - Amsterdam, The Netherlands : Elsevier. - 0167-9260 .- 1872-7522. ; 44:3, s. 229-241
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a digital background calibration technique that measures and cancels offset, linear and nonlinear errors in each stage of a pipelined analog to digital converter (ADC) using a single algorithm. A simple two-step subranging ADC architecture is used as an extra ADC in order to extract the data points of the stage-under-calibration and perform correction process without imposing any changes on the main ADC architecture which is the main trend of the current work. Contrary to the conventional calibration methods that use high resolution reference ADCs, averaging and chopping concepts are used in this work to allow the resolution of the extra ADC to be lower than that of the main ADC.
|
|
| 2. |
- Jalili, Armin, et al.
(författare)
-
Calibration of high-resolution flash ADCS based on histogram test methods
- 2010
-
Ingår i: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on. - : IEEE. - 9781424481552 ; , s. 114-117
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.
|
|
| 3. |
- Jalili, Armin, et al.
(författare)
-
Calibration of sigma-delta analog-to-digital converters based on histogram test methods
- 2010
-
Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
-
Konferensbidrag (refereegranskat)abstract
- In this paper we present a calibration technique for sigma-delta analog-to-digital converters (ΣΔADC) in which highspeed, low-resolution flash subADCs are used. The calibration technique as such is mainly targeting calibration of the flash subADC, but we also study how the correction depends on where in the ΣΔ modulator the calibration signals are applied. It is shown that the calibration technique can cope with errors that occur in the feedback digital-to-analog converter (DAC) and the input accumulator. Behavioral-level simulation results show an improvement of in effective number of bits (ENOB) from 6.6 to 11.3. Fairly large offset and gain errors have been introduced which illustrates a robust calibration technique.
|
|
