| 1. |
- Gong, Shaofang, 1960-, et al.
(författare)
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Design of a radio front-end module at 5 GHz
- 2004
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Ingår i: 6th Circuits and System Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication,2004. - Piscataway, CA, USA : IEEE. ; , s. 241-
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Konferensbidrag (refereegranskat)
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| 2. |
- Gong, Shaofang, et al.
(författare)
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Radio Architecture for Parallel Processing of Extremely High Speed Data
- 2009
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Ingår i: IEEE International Conference on Ultra-Wideband, ICUWB, Vancouver, Canada, 9-11 Sept.. - : IEEE. - 9781424429301 ; , s. 433-437
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Konferensbidrag (refereegranskat)abstract
- Using our own-developed frequency multiplexing network, a radio architecture for parallel radio signal processing has been proposed for achieving extremely high data rate above 10 Gbit/s. To meet the high requirement on phase linearity, amplitude balance and low noise figure in a very large bandwidth, our own-developed ultra-wideband six-port correlator has been utilized for the modulator and demodulator in the radio architecture.
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| 3. |
- Gong, Shaofang, 1960-, et al.
(författare)
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Six-port Modulators for High Speed Data
- 2016
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Ingår i: GigaHertz Symposium 2016. - Linköping. ; , s. 65-
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Konferensbidrag (refereegranskat)abstract
- Results from our recent study on six-port modulators and demodulators for high speed data transmission have shown that the six-port radio technology has the potential to catch up the speed of the Internet. This is due to the fact that the binary baseband data, either electrical or optical, can be converted directly to high order modulated RF signal without any D/A conversion. The six-port modulators and demodulators can also be designed with differential circuitry to improve the signal-to-noise ration and dynamic range. In addition, antennae and radio front-end components can be integrated on the same substrate with the six-port modulator and demodulator.
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| 4. |
- Gong, Shaofang, et al.
(författare)
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Truly Differential RF and Microwave Front-End Design
- 2010
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Ingår i: IEEE 11th Annual Wireless and Microwave Technology Conference (WAMICON). - Piscataway, NJ, USA : IEEE. - 9781424466887 ; , s. 1-5
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Konferensbidrag (refereegranskat)abstract
- New design methodology for truly differential RF and microwave front-ends has been presented in this paper. Baluns are avoided using this design methodology, while achieving differential signaling for high noise immunity. A case study on an ultra-wide band RF front-end in the frequency band 6-9 GHz has been performed using the new design methodology, indicating that both wide bandwidth and high performance can be achieved using this design methodology. A direct comparison between single-ended and differential designs of the RF filter has also been presented in order to verify the correctness of the design methodology.
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| 5. |
- Jakobsson, Anders, et al.
(författare)
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A Low Noise RC-based Phase Interpolator in 16-nm CMOS
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 66:1
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Tidskriftsartikel (refereegranskat)abstract
- This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm2.
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| 6. |
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| 7. |
- Jakobsson, Anders, et al.
(författare)
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Frequency Synthesizer With Dual Loop Frequency and Gain Calibration
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 60:11, s. 2911-2919
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Tidskriftsartikel (refereegranskat)abstract
- A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 $mu$ m CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain ($K_{rm VCO}$ of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 $mu$s including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is ${-}123$ dBc/Hz and the integrated phase error (1 kHz–2 MHz) is 1.26 $^{circ}$.
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| 8. |
- Jakobsson, Anders, et al.
(författare)
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Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS
- 2015
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE Computer Society. - 1549-8328 .- 1558-0806. ; 62:3, s. 680-688
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Tidskriftsartikel (refereegranskat)abstract
- A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 um CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.
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| 9. |
- Jakobsson, Anders
(författare)
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On PLL Modeling and Design in Nanometer‐Scale CMOS
- 2022
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Integrated circuits play a vital role in our everyday lives, from wireless gadgets and multimedia players to sensors and processors that control vital infrastructure. Since most electronic circuits need a clean, stable clock or carrier to function, one of the most important components of integrated circuits is the phase-locked loop. The performance metrics of the phase-locked loop, such as output frequency and range, phase noise, power consumption as well as development and manufacturing costs, all have a great impact on the circuit it serves. Hence, a lot of research has been conducted with the aim to improve its performance. While phase-locked loop performance has increased by orders of magnitude over its 90-year-old history, there is still more to be done. The aim of this thesis is to continue the strive for better performance.The thesis covers four topics of phase-locked loop design; modeling, calibration, fractional division and the fractional-N sub-sampling phase-locked loop. Apart from the sub-sampling phaselocked loop, only analog Type-II phase-locked loops are considered. The structure of the thesis is as follows. Chapter 2 covers the basics of phase-locked loop theory, such as system metrics, components, dynamics and phase noise. Readers who are familiar with analog phase-locked loops may wish to skip this chapter.Chapter 3 discusses state-of-the-art phase-locked loop time-domain models. An improved model implementation based on a quantized-state system is introduced with reference to Paper II, where it is shown how this can be implemented in Verilog-AMS. This type of model is ideal for phase-locked loop modeling as it is fully event-based, yet is still able to solve the ordinary differential equations of the loop filter. Improvements on the model presented in Paper II are also discussed.Chapter 4 looks at phase-locked loop frequency calibration for multi-band voltage-controlled oscillators, as well as gain calibration. A novel method for calibrating both frequency and gain, presented in Paper I, is introduced. This method allows for reduced calibration time without the need to resort to high-speed counters or complex analog circuitry. A simple bang-bang phase detector and a proportional/integral-controller are used to close the calibration loop. Furthermore, the voltage-controlled oscillator tuning voltage is initialized without the use of switches in the loop filter. Further improvements to this method are also presented.Chapter 5 discusses attempts to suppress sigma-delta noise, and the need for a truly fractional divider. State-of-the-art methods for fractional division are described and discussed. A novel RC-based phase interpolator is introduced with reference to Paper III. This phase interpolator is based on the method of constant-slope charging using current mirrors, but instead uses an inverse exponential charging curve. The phase interpolator unit is built from passive components and switches, which is well suited for nanometer-scale CMOS. The lack of current mirrors also reduces noise. The chapter finishes with presenting measurement results of an improved implementation.Chapter 6 combines the methods and circuits proposed in Chapters 3-5 to model and analyse a fractional-N sub-sampling phase-locked loop. The phase-locked loop is analysed from a system perspective, proving that the introduction of a divider does not degrade the superior charge pump noise performance often associated with sub-sampling phase-locked loops. Furthermore, an improved differential sampler is presented, with superior power supply rejection ratio. Finally, simulation results for the entire phase-locked loop is presented.
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| 10. |
- Karlsson, Magnus, 1977-, et al.
(författare)
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Circular Dipole Antennas for Lower and Upper UWB Bands with Integrated Balun
- 2009
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Ingår i: 2009 IEEEInternational Conference on Ultra-Wideband. - Vancover : IEEE. - 9781424429301 ; , s. 658-663
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Konferensbidrag (refereegranskat)abstract
- Abstract—Two fully integrated dipole antennas with balun for ultra-wideband (UWB) radio utilizing a flexible and rigid printed circuit board are presented in this paper. The concept in this paper is to take advantage of the respective possibilities of the rigid and the flexible part. The balun utilizes broadside-coupled microstrips and is integrated in the rigid part of the printed circuit board, while the radiator is placed in the flexible part. The lower UWB band antenna with the balun covers the frequency-band 3.1-4.8 GHz (with margin) at VSWR<2.0. The upper UWB band antenna with the balun covers the frequency-band 6.0-8.5 GHz (with margin) at VSWR<2.0, and 5.5-11.0 GHz at VSWR<2.5.
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