| 1. |
- Baghaei Nejad, Majid, et al.
(författare)
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UWB radio module design for wireless sensor networks
- 2007
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Ingår i: Analog Integrated Circuits and Signal Processing. - : Springer Science and Business Media LLC. - 0925-1030 .- 1573-1979. ; 50:1, s. 47-57
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 mu m CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SOP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight's helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than -10 dB over the UWB band.
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| 2. |
- Koivisto, Tero, et al.
(författare)
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Sine wave as a correlating signal for UWB radio
- 2006
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Ingår i: 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS. - NEW YORK, NY : IEEE. - 9780780393899 ; , s. 674-677
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Konferensbidrag (refereegranskat)abstract
- In this paper, an analog correlator for impulse radio is designed using a sine wave as a correlating signal. The design of the low-power sine wave generation circuitry is demonstrated and the analog multiplier using this waveform is implemented. The overall power consumption of the 8GHz LC-VCO and the divider-by-two circuit is 5mW.
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| 3. |
- Michielsen, Wim, et al.
(författare)
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Performance and cost estimations of packaged single band Voltage Controlled Oscillators
- 2004
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Ingår i: PROCEEDINGS OF THE IEEE 6TH CIRCUITS AND SYSTEMS SYMPOSIUM ON EMERGING TECHNOLOGIES: FRONTIERS OF MOBILE AND WIRELESS COMMUNICATION, VOLS 1 AND 2. - NEW YORK : IEEE. - 0780379381 ; , s. 53-56
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Konferensbidrag (refereegranskat)abstract
- This paper reports the performance and cost estimations in the early stage of a LC tank based Voltage Controlled Oscillator (VCO) design. System-on-Chip (SoC) versus System-on-package (SoP) configurations is compared for electrical performance and cost of a 1.25 GHz voltage controlled oscillator. It is found that a single chip design is not always the best solution. We obtained the best figure of merit for a SoP implementation where only the inductors were put off-chip.
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| 4. |
- Peltonen, Teemu, et al.
(författare)
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A 0.18 #x003BC;m CMOS Ultra-Wideband Low-Noise Amplifier with High IIP3
- 2005
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Ingår i: Proceedings of the Seventh IEEE CPMT Conference on High Density Microsystem Design, Packaging and Failure Analysis (HDP'05). ; , s. 452-454
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Konferensbidrag (refereegranskat)abstract
- In this paper an ultra-wideband low-noise amplifier (LNA) for the frequency range of 3.1 - 9.4 GHz using 0.18 mu m CMOS RF process is introduced. Single-ended single stage LNA structure utilises an input LC-ladder, cascode transistor configuration and LRC-feedback to realise an ultra broad bandwidth response. In operating frequency range noise figure (NF) of 3.1 dB and gain of 10.6 dB were achieved along with high linearity (IIP3) even upto 10.9 dBm at 3.1 GHz. With the bias network, the LNA had a total power consumption of 31 mW from 1.8 V supply.
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| 5. |
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| 6. |
- Shen, Meigen, et al.
(författare)
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Case study of interconnect analysis for standing wave oscillator design
- 2005
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Ingår i: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS. ; , s. 456-459
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Konferensbidrag (refereegranskat)abstract
- As a result of continuous downscaling CMOS technology, on-chip interconnects play critical role in highspeed circuits design. In this paper, geometry based accurate circuit model of interconnect is extracted for high-speed circuits design and analysis. This is demonstrated through a 10GHz standing wave oscillator (SWO) for global clock distribution. The results show that the skew of the clock is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. Hence, for high-speed circuits, the parameters of interconnect should be predictable according to its geometry in order to avoid design iterations and speed time-to-market. Meanwhile, robust circuit architectures should be adopted for tolerating the parameters variation of interconnects.
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| 7. |
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| 8. |
- Shen, Meigen, et al.
(författare)
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Chip-package co-design for high performance and reliability off-chip communications
- 2004
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Ingår i: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04). - NEW YORK : IEEE. - 0780386205 ; , s. 31-36
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Konferensbidrag (refereegranskat)abstract
- Low interaction between chip and package has more and more limited system performance. In this paper, chip-package co-design methodology is presented. We address high performance and reliability enhancement for off-chip communications under package and interconnection constraints by using impedance control, optimal package pins assignment and transmitter equalization. From the high-speed transmitter design example, it is shown that the system-level performances such as signal integrity, bandwidth, and reliability are significantly improved through this co-design methodology.
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| 9. |
- Shen, Meigen, 1970-
(författare)
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Concurrent chip and package design for radio and mixed-signal systems
- 2005
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The advances in VLSI and packaging technologies enable us to integrate a whole system on a single chip (SoC) or on a package module. In these systems, analog/RF electronics, digital circuitries, and memories coexist. This new technology brings us new freedom for system integration as well as new challenges in system design and implementation. To fully utilize the benefits of these new hardware technologies, concurrent design of system, chip, and package is necessary. This research aims to explore the new design space and opportunities for System-on-Package (SoP), with special attention on radio and mixed-signal system applications. Global level system partitioning for SoC and SoP with cost-performance trade-off, concurrent chip and design for high-speed off-chip signaling, global clock distribution, and ultra wideband (UWB) radio module are two fields in this research.Cost-performance driven for mixed-signal system partitioning in early conceptual level design is first addressed in this thesis. We develop a modeling technique to pre-estimate the cost and performance. The performance model evaluates various noise isolation technologies, such as using guard rings, and partitioning the system into several chips. In cost analysis, new factors such as extra chip area and additional process steps due to mixed signal isolation, integration of intellectual property (IP) right module or “virtual components”, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip are considered. An efficient computation algorithm, namely COMSI, is developed for cost estimation under various mixed-signal performance constraints.System interconnect topologies have been moving away from multi-point bus architecture and towards high-speed serial links. But low interaction between chip and package design has more and more limited system performance. We address concurrent chip and package design and co-optimization for high-speed off-chip signaling in this part. First we explore the interconnect and package constraints to the circuit and system architecture. Proper equivalent circuit models for package parasitics are set up and then a 3-dimension electromagnetic (EM) solver is used to extract the parasitic parameters of package. After that, bandwidth and noise of the signal channel are estimated. The optimal off-chip singling is designed according to these packages and interconnection constraints. We also analyzed the global clock distribution using co-design method.We developed a low cost, low power consumption, and low complexity UWB radio module using co-design method and SoP technologies. The module will be used in low data rate and long-range wireless intelligent systems such as radio frequency identification (RFID) or wireless sensors networks (WSN). Liquid-crystal-polymer (LCP) based SoP technologies were used to implement the module.
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| 10. |
- Shen, Meigen, et al.
(författare)
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Concurrent chip-package design for 10GHz global clock distribution network
- 2005
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Ingår i: 55th Electronic Components & Technology Conference, Vols 1 and 2, 2005 Proceedings. - 0780389069 ; , s. 1554-1559
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Konferensbidrag (refereegranskat)abstract
- As a result of the continuous downscaling of the CMOS technology, on chip frequency for high performance microprocessor will soon arrive 10GHz according to international technology roadmap for semiconductors (ITRS). In this paper, a 10GHz global clock distribution network using standing wave approach was analyzed on chip and package level. On chip level, a 10GHz standing wave oscillator (SWO) for global clock distribution network using 0.18um, 1P6M CMOS technology, is designed and analyzed. The simulation results show that the skew is well controlled (about 1ps) while the clock frequency variation is about 20% because power/ground return paths exist in different metal layers. On package level, we assume that the chip size is 20mm*20mm and flip-chip bonding technology is used. The simulation results show that the skew at random positions of the transmission line (spiral or serpentine shape) is within 10% of tau(clk) when the attenuation is about 1.5dB. For attenuation from 1.5dB to 6.7dB, the peak positions (n*lambda/2) can be used as clock node. For the mesh and plane shape, the skew is controlled within 10% of tau(clk) using standing wave method.
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