| 1. |
- Broman, David, et al.
(författare)
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Precision Timed Infrastructure : Design Challenges
- 2013
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Ingår i: Proceedings of the Electronic System Level Synthesis Conference (ESLsyn). - : IEEE conference proceedings. - 9781467364140
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Konferensbidrag (refereegranskat)abstract
- In general-purpose software applications, computation time is just a quality factor: faster is better. In cyber-physical systems (CPS), however, computation time is a correctness factor: missed deadlines for hard real-time applications, such as avionics and automobiles, can result in devastating, life-threatening consequences. Although many modern modeling languages for CPS include the notion of time, implementation languages such as C lack any temporal semantics. Consequently, models and programs for CPS are neither portable nor guaranteed to execute correctly on the real system; timing is merely a side effect of the realization of a software system on a specific hardware platform. In this position paper, we present the research initiative for a precision timed (PRET) infrastructure, consisting of languages, compilers, and microarchitectures, where timing is a correctness factor. In particular, the timing semantics in models and programs must be preserved during compilation to ensure that the behavior of real systems complies with models. We also outline new research and design challenges present in such an infrastructure.
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| 3. |
- Kim, Hokeun, et al.
(författare)
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A Predictable and Command- Level Priority-Based DRAM Controller for Mixed-Criticality Systems
- 2015
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Ingår i: Proceedings of the 21th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). - : IEEE Press. - 9781479986033 ; , s. 317-326
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Konferensbidrag (refereegranskat)abstract
- Mixed-criticality systems have tasks with different criticality levels running on the same hardware platform. Today's DRAM controllers cannot adequately satisfy the often conflicting requirements of tightly bounded worst-case latency for critical tasks and high performance for non-critical real-time tasks. We propose a DRAM memory controller that meets these requirements by using bank-aware address mapping and DRAM command-level priority-based scheduling with preemption. Many standard DRAM controllers can be extended with our approach, incurring no performance penalty when critical tasks are not generating DRAM requests. Our approach is evaluated by replaying memory traces obtained from executing benchmarks on an ARM ISA-based processor with caches, which is simulated on the gem5 architecture simulator. We compare our approach against previous TDM-based approaches, showing that our proposed memory controller achieves dramatically higher performance for non-critical tasks, without any significant impact on the worstcase latency of critical tasks.
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