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- Björk, Magnus, 1977, et al.
(författare)
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Exposed Datapath for Efficient Computing
- 2006
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- We introduce FlexCore, which is the first exemplar of a processor based on the FlexSoC processor paradigm. TheFlexCore utilizes an exposed datapath for increased performance. Microbenchmarks yield a performance boost of a factor of two over a traditional five-stage pipeline with the same functional units as the FlexCore.We describe our approach to compiling for the FlexCore.A flexible interconnect allows the FlexCore datapath to bedynamically reconfigured as a consequence of code generation. Additionally, specialized functional units may be introduced and utilized within the same architecture and compilation framework. The exposed datapath requires a wide control word. The conducted evaluation of two micro benchmarks confirms that this increases the instruction bandwidth and memory footprint. This calls for an efficient instruction decoding as proposed in the FlexSoC paradigm.
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| 3. |
- Dahlen, Torsten, et al.
(författare)
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Cardiovascular Events Associated With Use of Tyrosine Kinase Inhibitors in Chronic Myeloid Leukemia : A Population-Based Cohort Study
- 2016
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Ingår i: Annals of Internal Medicine. - Karolinska Univ Hosp, Stockholm, Sweden. Karolinska Inst, Stockholm, Sweden. Reg Canc Ctr, Uppsala, Sweden. Univ Uppsala Hosp, Uppsala, Sweden. Umea Univ, Umea, Sweden. Skane Univ Hosp, Lund, Sweden. [Dahlen, Torsten; Bjorkholm, Magnus; Ohm, Lotta; Stenke, Leif] Karolinska Univ Hosp Solna, Div matol, Dept Med, SE-17176 Stockholm, Sweden. [Edgren, Gustaf; Lambe, Mats] Karolinska Inst, Dept Med Epidemiol & Biostat, SE-17177 Stockholm, eden. [Hoglund, Martin; Olsson-Stromberg, Ulla] Univ Hosp, Dept Med Sci, SE-75185 Uppsala, Sweden. [Hoglund, Martin; Olsson-Stromberg, Ulla] Univ Hosp, Div Hematol, SE-75185 Uppsala, Sweden. [Sandin, Fredrik] Uppsala Univ Hosp, Reg Canc Ctr, SE-75185 Uppsala, Sweden. [Sjalander, Anders] Umea Univ, Dept Publ Hlth & Clin Med, SE-90185 Umea, Sweden. [Richter, Johan] Skane Univ Hosp, Dept Hematol & Vasc Disorders, SE-22241 Lund, Sweden. [Back, Magnus] Karolinska Univ Hosp, Dept Cardiol, SE-17176 Stockholm, Sweden.. - 0003-4819 .- 1539-3704. ; 165:3, s. 161-166
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Tidskriftsartikel (refereegranskat)abstract
- Background: Tyrosine kinase inhibitors (TKIs) have increased survival dramatically for patients with chronic myeloid leukemia (CML), but continuous administration of these drugs may elicit long-term toxicity.Objective: To investigate the incidence of vascular events in patients with CML treated with first-and second-generation TKIs.Design: Retrospective cohort study using nationwide population-based registries.Setting: Sweden.Patients: All patients diagnosed with chronic-phase CML in Sweden from 2002 to 2012 and treated with a TKI, and 5 age- and sex-matched control individuals per patient.Measurements: Relative risks, expressed as incidence rate ratios comparing patients with control individuals, were calculated. Events per 1000 person-years were assessed in interdrug comparisons.Results: 896 patients, 94.4% with documented TKI treatment, were followed for a median of 4.2 years. There were 54 arterial and 20 venous events in the CML cohort, corresponding to relative risks of 1.5 (95% CI, 1.1 to 2.1) and 2.0 (CI, 1.2 to 3.3), respectively. The event rate for myocardial infarction was higher in patients treated with nilotinib or dasatinib (29 and 19 per 1000 person-years, respectively) than in those receiving imatinib (8 per 1000 person-years), although data are limited and the CIs were wide and overlapped. Among 31 patients treated with a TKI who had myocardial infarction, 26 (84%) had at least 1 major cardiac risk factor diagnosed before the event occurred.Limitations: Patients may have been exposed to multiple TKIs. Data on second-and third-generation TKIs were limited.Conclusion: An increased risk for arterial and venous vascular events was seen in patients with CML treated with a TKI. Further study is needed to determine whether the risk for myocardial infarction increases with second-generation drugs.
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| 5. |
- Själander, Magnus, 1977, et al.
(författare)
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A Flexible Datapath Interconnect for Embedded Applications
- 2007
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Ingår i: IEEE Computer Society Annual Symposium on VLSI. ; , s. 15-20
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Konferensbidrag (refereegranskat)abstract
- We investigate the effects of introducing a flexible interconnect into an exposed datapath. We define an exposed datapath as a traditional GPP datapath that has its normal control removed, leading to the exposure of a wide control word. For an FFT benchmark, the introduction of a flexible interconnect reduces the total execution time by 16%. Compared to a traditional GPP, the execution time for an exposed datapath using a flexible interconnect is 32% shorter whereas the energy dissipation is 29% lower. Our investigation is based on a cycleaccurate architectural simulator and figures on delay, power, and area are obtained from placed-and-routed layouts in a commercial 0.13-ìm technology. The results from our case studies indicate that by utilizing a flexible interconnect, significant performance gains can be achieved for generic applications.
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| 7. |
- Thuresson, Martin, 1977, et al.
(författare)
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FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
- 2009
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Ingår i: Journal of Signal Processing Systems. - : Springer Science and Business Media LLC. - 1939-8018 .- 1939-8115. ; 57:1, s. 5-19
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Tidskriftsartikel (refereegranskat)abstract
- We introduce FlexCore, the first exemplar of an architecture based on the FlexSoC framework. Comprising the same datapath units found in a conventional five-stage pipeline, the FlexCore has an exposed datapath control and a flexible interconnect to allow the datapath to be dynamically reconfigured as a consequence of code generation. Additionally, the FlexCore allows specialized datapath units to be inserted and utilized within the same architecture and compilation framework.This study shows that, in comparison to a conventional five-stage general-purpose processor, the FlexCore is up to 40\% more efficient in terms of cycle count on a set of benchmarks from the embedded application domain. We show that both the fine-grained control and the flexible interconnect contribute to the speedup. Furthermore, our synthesized, placed and routed FlexCore offers savings both in energy and execution time.The exposed FlexCore datapath requires a wide control word. The conducted evaluation confirms that this increases the instruction bandwidth and memory footprint. This calls for efficient instruction decoding as proposed in the FlexSoC framework.
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| 8. |
- Aimoniotis, Pavlos, et al.
(författare)
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Data-Out Instruction-In (DOIN!) : Leveraging Inclusive Caches to Attack Speculative Delay Schemes
- 2022
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Ingår i: 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED 2022). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781665485265 - 9781665485272 ; , s. 49-60
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Konferensbidrag (refereegranskat)abstract
- Although the cache has been a known side-channel for years, it has gained renewed notoriety with the introduction of speculative side-channel attacks such as Spectre, which were able to use caches to not just observe a victim, but to leak secrets. Because the cache continues to be one of the most exploitable side channels, it is often the primary target to safeguard in secure speculative execution schemes. One of the simpler secure speculation approaches is to delay speculative accesses whose effect can be observed until they become non-speculative. Delay-on-Miss, for example, delays all observable speculative loads, i.e., the ones that miss in the cache, and preserves the majority of the performance of the baseline (unsafe speculation) by executing speculative loads that hit in the cache, which were thought to be unobservable.However, previous work has failed to consider how instruction fetching can eject cache lines from the shared, lower level caches, and thus from higher cache levels due to inclusivity. In this work, we show how cache conflicts between instruction fetch and data accesses can extend previous attacks and present the following new insights:1. It is possible to use lower level caches to perform Prime+Probe through conflicts resulting from instruction fetching. This is an extension to previous Prime+Probe attacks that potentially avoids other developed mitigation strategies.2. Data-instruction conflicts can be used to perform a Spectre attack that breaks Delay-on-Miss. After acquiring a secret, secret-dependent instruction fetching can cause cache conflicts that result in evictions in the L1D cache, creating observable timing differences. Essentially, it is possible to leak a secret bit-by-bit through the cache, despite Delay-on-Miss defending against caches.We call our new attack Data-Out Instruction-In, DOIN!, and demonstrate it on a real commercial core, the AMD Ryzen 9. We demonstrate how DOIN! interacts with Delay-on-Miss and perform an analysis of noise and bandwidth. Furthermore, we propose a simple defense extension for Delay-on-Miss to maintain its security guarantees, at the cost of negligible performance degradation while executing the Spec06 workloads.
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| 9. |
- Aimoniotis, Pavlos, et al.
(författare)
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ReCon : Efficient Detection, Management, and Use of Non-Speculative Information Leakage
- 2023
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Ingår i: 56th IEEE/ACM International Symposium on Microarchitecture, MICRO 2023. - : Association for Computing Machinery (ACM). - 9798400703294 ; , s. 828-842
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Konferensbidrag (refereegranskat)abstract
- In a speculative side-channel attack, a secret is improperly accessed and then leaked by passing it to a transmitter instruction. Several proposed defenses effectively close this security hole by either delaying the secret from being loaded or propagated, or by delaying dependent transmitters (e.g., loads) from executing when fed with tainted input derived from an earlier speculative load. This results in a loss of memory-level parallelism and performance. A security definition proposed recently, in which data already leaked in non-speculative execution need not be considered secret during speculative execution, can provide a solution to the loss of performance. However, detecting and tracking non-speculative leakage carries its own cost, increasing complexity. The key insight of our work that enables us to exploit non-speculative leakage as an optimization to other secure speculation schemes is that the majority of non-speculative leakage is simply due to pointer dereferencing (or base-address indexing) - essentially what many secure speculation schemes prevent from taking place speculatively. We present ReCon that: i) efficiently detects non-speculative leakage by limiting detection to pairs of directly-dependent loads that dereference pointers (or index a base-address); and ii) piggybacks non-speculative leakage information on the coherence protocol. In ReCon, the coherence protocol remembers and propagates the knowledge of what has leaked and therefore what is safe to dereference under speculation. To demonstrate the effectiveness of ReCon, we show how two state-of-the-art secure speculation schemes, Non-speculative Data Access (NDA) and speculative Taint Tracking (STT), leverage this information to enable more memorylevel parallelism both in a single core scenario and in a multicore scenario: NDA with ReCon reduces the performance loss by 28.7% for SPEC2017, 31.5% for SPEC2006, and 46.7% for PARSEC; STT with ReCon reduces the loss by 45.1%, 39%, and 78.6%, respectively.
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| 10. |
- Azhar, Muhammad Waqar, 1986, et al.
(författare)
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Viterbi Accelerator for Embedded Processor Datapaths
- 2012
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Ingår i: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. - 1063-6862. - 9780769547688 ; , s. 133-140
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Konferensbidrag (refereegranskat)abstract
- We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an embedded processor. We investigate the accelerator’s impact on processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s.
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