| 1. |
- Tobin, Stephen, et al.
(författare)
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Nondestructive Assay Data Integration with the SKB-50 Assemblies - FY16 Update
- 2016
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- A project to research the application of non-destructive assay (NDA) techniques for spent fuel assemblies is underway at the Central Interim Storage Facility for Spent Nuclear Fuel (for which the Swedish acronym is Clab) in Oskarshamn, Sweden. The research goals of this project contain both safeguards and non-safeguards interests. These nondestructive assay (NDA) technologies are designed to strengthen the technical toolkit of safeguard inspectors and others to determine the following technical goals more accurately; Verify initial enrichment, burnup, and cooling time of facility declaration for spent fuel assemblies; Detect replaced or missing pins from a given spent fuel assembly to confirm its integrity; and Estimate plutonium mass and related plutonium and uranium fissile mass parameters in spent fuel assemblies. Estimate heat content, and measure reactivity (multiplication).
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| 2. |
- Abdulaziz, Mohammed, 1983, et al.
(författare)
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A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS
- 2019
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 67:4, s. 1588-1600
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Tidskriftsartikel (refereegranskat)abstract
- © 2019 IEEE. This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm 2 . The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between-93 and-96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of-245 dB. The lock time in low-noise mode is up to 12μs, which is improved to 3μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between-235 and-240 dB.
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| 3. |
- Abdulaziz, Mohammed, et al.
(författare)
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A 3.4mW 65nm CMOS 5th Order Programmable Active-RC Channel Select Filter for LTE Receivers
- 2013
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Ingår i: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2013. - 1529-2517. - 9781467360593 ; , s. 217-220
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Konferensbidrag (refereegranskat)abstract
- In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm CMOS technology with a core area of 0.29mm2. Its total current consumption is 2.83mA from a 1.2V supply. The measured input referred noise is 39nV/ √ Hz, the in-band IIP3 is 21.5dBm, at the band-edge the IIP3 is 20.7dBm, the out-of-band IIP3 is 20.6dBm, and the compression point is 0dBm.
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| 4. |
- Abdulaziz, Mohammed, et al.
(författare)
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A 4th Order Gm-C Filter with 10MHz Bandwidth and 39dBm IIP3 in 65nm CMOS
- 2014
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Ingår i: [Host publication title missing]. - 1930-8833. ; , s. 367-370
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Konferensbidrag (refereegranskat)abstract
- Gm-C filters suffer from limited dynamic range due to a trade-off between noise and linearity in OTA design. This paper therefore presents a filter with a linearization technique to break this trade-off. This technique is demonstrated by a low power 4th order 10MHz Butterworth Gm-C low pass filter. The filter was implemented in 65nm CMOS technology with a core area of 0.19mm2 and a total current consumption of 3.5mA from a 1.2V supply. The measured input referred noise is 31nV/√Hz, the maximum in-band IIP3 is 39dBm, the out-of-band IIP3 is 34dBm, and the compression point is 8.2dBm.
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| 5. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Cellular Receiver Front-End with Blocker Sensing
- 2016
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Ingår i: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016. - 9781467386517
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Konferensbidrag (refereegranskat)abstract
- A receiver front-end supporting contiguous and non-contiguous intra-band carrier aggregation scenarios with a fully integrated spectrum sensor that can detect both in-gap and out-of-band blockers has been implemented in 65nm CMOS technology. An NF of 2.5dB is achieved using a noise canceling LNTA, and linearized OTAs are used to achieve an IIP3 improvement of up to 6.5dB in-band and 11dB at the filter band edge. The spectrum sensor can detect blocker levels in 22 steps of 9MHz between -100MHz and 100MHz IF. The system consumes between 36.6mA and 57.6mA from a 1.2V supply.
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| 6. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Compensation Technique for Two-Stage Differential OTAs
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:8, s. 594-598
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Tidskriftsartikel (refereegranskat)abstract
- In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values which makes it attractive for low power applications with low area overhead.
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| 7. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Linearization Technique for Differential OTAs
- 2017
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 64:9, s. 1002-1006
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an operational transconductance amplifier (OTA) linearization technique that is applied to a low-noise amplifier (LNA) and an OTA-C filter. Simulations show the effectiveness of the proposed technique on the LNA, whose noise and gain performance remain unaffected while the linearity is significantly improved. Measurements of the 80-MHz fourth order Butterworth OTA-C filter are also presented. It is implemented using six OTAs instead of eight, thus reducing the power consumption and area. The filter is implemented in 65-nm low-power CMOS, with a core area of 0.05 mm 2 and consumes 12.6 mA from 1.2 V supply. The measured in-band noise voltage is below 42 nV/ Hz‾‾‾√ , and the measured third order intercept point improvement using OTA linearization is up to 17 dB in-band and about 3 dB out-of-band. Supply and temperature variation measurements on three samples show that the linearization is effective without a need for bias adjustment.
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| 8. |
- Ahmad, Waqas, et al.
(författare)
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A Fully Integrated 26dBm Linearized RF Power Amplifier in 65nm CMOS Technology
- 2015
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Konferensbidrag (refereegranskat)abstract
- In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm 2 of chip area.
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| 9. |
- Ahmad, Waqas, et al.
(författare)
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A Fully Integrated Radio-Fiber Interface in 65 nm CMOS Technology
- 2014
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Ingår i: IEEE Photonics Technology Letters. - 1041-1135. ; 26:5, s. 444-446
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Tidskriftsartikel (refereegranskat)abstract
- In this work we present a fully integrated Radio-Fiber interface implemented in 65nm CMOS, intended for remote antenna units (RAUs) in distributed antenna systems. To relax the requirements on the optical components, an intermediate frequency (IF) signal (100MHz) is transmitted over the multi-mode fiber, which is then up-converted to 2.2GHz inside the RAU. Local Oscillator (LO) signals to the mixers are generated by an on-chip frequency synthesizer. The measured optical to electrical conversion gain\,(V/W) is 59\,dB, whereas the input referred current noise is 3.5pA/$\sqrt{\mathrm{Hz}}$ and SFDR is 96.5dBHz^2/3. An LO leakage of -40dBc and an image rejection ratio of 43\,dB is measured. The circuit achieves an adjacent channel leakage ratio (ACLR) of -39dB and -41dB, for a 10MHz 32QAM signal at output power of 1dBm, and a 3.84MHz QPSK signal at 4dBm, respectively.
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| 10. |
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