| 1. |
- Abdulaziz, Mohammed, et al.
(författare)
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Improving Receiver Close-In Blocker Tolerance by Baseband Gm-C Notch Filtering
- 2019
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328. ; 66:3, s. 885-896
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offset frequency, and the measurements indicate a significant improvement in the overall front-end interference robustness, while sensitivity remains unaffected. To optimize notch performance, the BB impedance is analyzed in detail. The front-end RF range is 750 MHz-3 GHz with an RF channel bandwidth of 20 MHz corresponding to 10-MHz BB bandwidth. The notch frequency is programmable from 16, which is less than one octave from the channel edge, up to 160 MHz. The gain-compression improvement is upto 9 dB, while IIP2 can be increased by more than 26 dB without calibration and IIP3 is 1 dBm. The current overhead for the notch function is between 7.5 and 30 mA, but it only exists under strong blocker conditions as the notch filter can be switched off if strong blockers are absent. The total front-end current consumption excluding the notch filter varies with LO frequency from 31 to 44 mA from a 1.2-V supply.
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| 2. |
- Bagger, Reza, et al.
(författare)
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A 20-GHz Bandwidth Power Amplifier for Phased Array 5G New Radio Transmitters
- 2020
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Ingår i: IEEE Solid-State Circuits Letters. - 2573-9603. ; 3, s. 302-305
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Tidskriftsartikel (refereegranskat)abstract
- A 27-47-GHz differential cascode power amplifier for millimeter-wave 5G new radio applications is presented. The PA is a three-stage design using inductively coupled impedance transformers with 31-dB nominal power gain. A device periphery ratio of 1:2:6 is adopted for predriver, driver, and final stage, respectively. A gain equalization technique was used in the interstage transformers to obtain the required bandwidth with high gain flatness. To enable the use of 2.7-V supply, a cascode topology was employed in all three stages. A small signal gain of 31 dB was achieved with a 3-dB bandwidth of 20 GHz, equivalent to a 54% fractional bandwidth centered at 37 GHz. A saturated output power of 20.6 dBm was measured at 38.5 GHz. With a 100-MHz 64-QAM OFDM modulated signal at 37 GHz and at EVM =-25 dB, an output power of 11.6 dBm and an ACLR1 of-32/-30.8 dBc were obtained. An SiGe HBT BiCMOS process with f_{\mathrm{ MAX}} = 330 GHz was used for fabrication. The PA has an active area of 0.28 mm2 and is measured to a best in class FOM of 94.7 dB.
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| 3. |
- Bagger, Reza, et al.
(författare)
-
A 20-GHz Bandwidth Power Amplifier for Phased Array 5G New Radio Transmitters
- 2020
-
Ingår i: IEEE Solid-State Circuits Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 2573-9603. ; 3, s. 302-305
-
Tidskriftsartikel (refereegranskat)abstract
- A 27-47-GHz differential cascode power amplifier for millimeter-wave 5G new radio applications is presented. The PA is a three-stage design using inductively coupled impedance transformers with 31-dB nominal power gain. A device periphery ratio of 1:2:6 is adopted for predriver, driver, and final stage, respectively. A gain equalization technique was used in the interstage transformers to obtain the required bandwidth with high gain flatness. To enable the use of 2.7-V supply, a cascode topology was employed in all three stages. A small signal gain of 31 dB was achieved with a 3-dB bandwidth of 20 GHz, equivalent to a 54% fractional bandwidth centered at 37 GHz. A saturated output power of 20.6 dBm was measured at 38.5 GHz. With a 100-MHz 64-QAM OFDM modulated signal at 37 GHz and at EVM =-25 dB, an output power of 11.6 dBm and an ACLR1 of-32/-30.8 dBc were obtained. An SiGe HBT BiCMOS process with f_{\mathrm{ MAX}} = 330 GHz was used for fabrication. The PA has an active area of 0.28 mm2 and is measured to a best in class FOM of 94.7 dB.
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| 4. |
- Bagger, Reza, et al.
(författare)
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An 11 GHz-Bandwidth Variable Gain Ka-Band Power Amplifier for 5G Applications
- 2019
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Ingår i: ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference. - 9781728115504 ; , s. 181-184
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Konferensbidrag (refereegranskat)abstract
- A Ka-band,32-43 GHz,differential power amplifier (PA) for millimeter wave applications is presented. The PA is a three stage design with a nominal gain of 36 dB. A device periphery ratio of 1:2:4 is adopted for pre-driver,driver and final stage,respectively. To enable use of 2.7 V supply,a cascode topology was employed in all three stages. The input is 80 ω differential and the output load is 50 ω single ended. The PA has a variable gain of 36 ± 11 dB for use as variable gain amplifier. A saturation power of 17.8 dBm was measured at 35 GHz with a small signal gain of 34.5 dB,including output losses of 2-2.5 dB over band. The design is based on magnetically coupled parallel resonators to obtain the required bandwidth. A SiGe HBT BiCMOS process with fMAX = 330 GHz was used for fabrication. The PA is part of a front-end design,and its output thus faces an antenna interface with integrated LNA and TX/RX switches,and the input is connected to an on-chip variable gain amplifier.
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| 5. |
- Bagger, Reza, et al.
(författare)
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An 11 GHz–Bandwidth Variable Gain Ka–Band Power Amplifier for 5G Applications
- 2019
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Ingår i: IEEE MTT-S International Microwave Symposium Digest. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 1950-1952
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Konferensbidrag (refereegranskat)abstract
- The performance of broadband microwave 40 W and 55 W LDMOS integrated power amplifiers is reported. A 30 V LDMOS process with 500 nm gate length was used for the design. Single and dual die packages were evaluated. A dual die package provides flexibility in output power and efficiency depending on combiner topology at the input and output of the circuit. Different saturated power and efficiency are obtained for different classes, Class A, AB and B operation and for different combiners, Wilkinson, quadrature or balun. Moreover, dual die in Doherty configuration provides a compact solution for better back-off efficiency in a symmetrical / asymmetrical topology. The 40 W design demonstrates 24 %, 1 dB fractional bandwidth around 2.1 GHz, and power added efficiency of 48 % at P-1 dB of 50 W. It showed excellent back-off linearity and best in class memory effect over frequency and temperature. The 55 W design has 28 %, 1 dB fractional bandwidth around 2.2 GHz, and power added efficiency of 49 % at P-1 dB equal to 63 W.
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| 6. |
- Bagger, Reza, et al.
(författare)
-
Broadband LDMOS 40 W and 55 W integrated power amplifiers
- 2017
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Ingår i: 2017 IEEE MTT-S International Microwave Symposium, IMS 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509063604 ; , s. 1950-1952
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Konferensbidrag (refereegranskat)abstract
- The performance of broadband microwave 40 W and 55 W LDMOS integrated power amplifiers is reported. A 30 V LDMOS process with 500 nm gate length was used for the design. Single and dual die packages were evaluated. A dual die package provides flexibility in output power and efficiency depending on combiner topology at the input and output of the circuit. Different saturated power and efficiency are obtained for different classes, Class A, AB and B operation and for different combiners, Wilkinson, quadrature or balun. Moreover, dual die in Doherty configuration provides a compact solution for better back-off efficiency in a symmetrical / asymmetrical topology. The 40 W design demonstrates 24 %, 1 dB fractional bandwidth around 2.1 GHz, and power added efficiency of 48 % at P-1 dB of 50 W. It showed excellent back-off linearity and best in class memory effect over frequency and temperature. The 55 W design has 28 %, 1 dB fractional bandwidth around 2.2 GHz, and power added efficiency of 49 % at P-1 dB equal to 63 W.
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| 7. |
- Dawji, Yunus, et al.
(författare)
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A 65-nm CMOS Low-Power Front-End for 3rd Generation DNA Sequencing
- 2019
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Ingår i: 2019 IEEE Sensors, SENSORS 2019 - Conference Proceedings. - 1930-0395 .- 2168-9229. - 9781728116341 ; 2019-October
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Konferensbidrag (refereegranskat)abstract
- A continuous-time, 65-nm CMOS, front-end for processing DNA sequencing measurements from biological nanopore sensors is presented. The measured design has an input referred noise floor of 8.5\;{\text{fA}}/\sqrt {{\text{Hz}}} for 100 pA DC current while consuming 10X less power. The chip also consists of an integrated ADC.
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| 8. |
- Ek, Staffan, et al.
(författare)
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A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
- 2018
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 53:7, s. 1988-2000
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Tidskriftsartikel (refereegranskat)abstract
- A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-antenna transceivers is presented. The system is modular with one phase locked loop (PLL) per antenna element transceiver, and a test circuit implemented in 28-nm fully depleted silicon on insulator (FD-SOI) CMOS features two such PLLs and a 491.52 MHz crystal oscillator (XO) generating a common frequency reference. A fractional-N architecture is employed to achieve high-frequency resolution, and the quantization noise is reduced using a novel frequency divider, which achieves full integer resolution while still using a pre-scaler. The system covers the 3rd Generation Partnership Project (3GPP) bands n257 and n258, achieved by a digital coarse tuning of the voltage-controlled oscillator (VCO). The chip area of each PLL is 0.11 mm², and 0.029 mm² for the XO. The total power consumption of the system is 35 mW, where each PLL consumes 15.4 mW and the XO consumes 0.84 mW. The total rms jitter from 20-kHz to 500-MHz offset for a 26-GHz carrier is just 115 fs, corresponding to an FOMj of -244 dB, which is the best reported figure for a fractional-N PLL above 15 GHz. The error-vector magnitude (EVM) due to phase noise is -34.6 dBc using an orthogonal frequency-division multiplexing (OFDM) signal with 120-kHz sub-carrier spacing, sufficient to support 256 QAM.
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| 9. |
- Elgaard, Christian, et al.
(författare)
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Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS
- 2024
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 59:2, s. 321-336
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Tidskriftsartikel (refereegranskat)abstract
- This article presents a fully integrated millimeter-wave (mmW) transceiver front end covering 24.25–29.5 GHz. It features a wideband Doherty power amplifier utilizing adaptive bias and a transmit/receive switch (TRX-switch) that has embedded low noise amplifier to antenna matching. The phase shift of 90 $^\circ$ to the Doherty auxiliary amplifier is achieved using a separate IQ-mixer with rearranged phases in the auxiliary path, ensuring a wideband 90 $^\circ$ phase shift, and avoiding 3-dB loss from radio frequency (RF) input power splitting. Special emphasis is on the analysis of adaptive bias, the Doherty output combiner network, the decoupling capacitors, and the TRX-switch. Including TRX-switch losses of 1.1 dB in transmit mode, the transmitter reaches a saturated output power of 18.3 dBm with a 1-dB output compression point of 15.9 dBm. Stimulated with a 400-MHz 16-QAM orthogonal frequency-division multiplexing (OFDM) IQ-signal at baseband, without digital IQ-compensation and predistortion, the transmitter delivers a 26.5-GHz modulated signal with an output power ( $P_{\rm out}$ ) of 12.8 dBm and an error vector magnitude (EVM) of $-$ 20.2 dB. The complete transmitter, including quadrature local oscillator drivers, then achieves a power added efficiency (PAE) of 5.8%. For a 1600-MHz wide 64-QAM OFDM signal, $P_{\rm out}$ is 9.0 dBm, with an EVM $=$ $-$ 23.3 dB and a complete transmitter PAE of 3.2%. In receive mode including TRX-switch, at 27.25 GHz, the noise figure is below 4 dB with a gain of 23 dB and a third-order input-referred intercept point of $-$ 9 dBm. The active part of the die, manufactured in 22-nm fully depleted silicon on insulator (FD-SOI) CMOS, occupies 2.3 mm $^2$ .
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| 10. |
- Gannedahl, Rikard, et al.
(författare)
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A mm-Wave Differential-to-Quadrature Frequency Tripler with Automatic Locking and Quadrature Correction
- 2023
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Ingår i: 2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings. - 9798350337570
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Konferensbidrag (refereegranskat)abstract
- This paper presents an injection-locked frequency tripler for 28-GHz direct-conversion transceivers, which takes a differential input and outputs a quadrature signal. A feedback system is added to ensure that lock occurs and to keep the quadrature error below 1° across operating frequencies and process corners. Simulations show that the tripler can cover the entire 24-30 GHz band across all corners, while consuming 32 mW from a 0.8 V supply. The circuit is designed and simulated in a 22nm FD-SOI CMOS process and occupies 0.2 mm2 active chip area.
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