| 1. |
- Fakih, Maher, et al.
(författare)
-
Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems
- 2019
-
Ingår i: Journal of Low Power Electronics and Applications. - : MDPI AG. - 2079-9268. ; 9:1
-
Tidskriftsartikel (refereegranskat)abstract
- With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication.
|
|
| 2. |
- Fritzin, Jonas, et al.
(författare)
-
Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
- 2010
-
Ingår i: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France. - : IEEE. - 9781424453085 ; , s. 1907-1910
-
Konferensbidrag (refereegranskat)abstract
- This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4–21.5dBm of output power with drain efficiencies and power-added efficiencies of 56–64% and 46–51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V, the output power dropped about 0.7dB.
|
|
| 3. |
- Qazi, Fahad, et al.
(författare)
-
A/D Conversion for Software Defined Radio
- 2010
-
Ingår i: Proceedings of the IEEE 6th Karlsruhe Workshop on Software Defined Radios 2010. ; , s. 70-76
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper we discuss possible variants of A/D conversion in multi-standard and pure software-defined radio (SDR) receiver architectures. The requirements for the ADC dynamic range and linearity are formulated for the contemporary personal and data-communication RF standards. Two implementation examples of a ADC in 90 nm and 65 nm CMOS are presented. These are a multi-bit first-order ADC aimed at baseband conversion and a one-bit second-order aimed at direct RF conversion, respectively. With limited channel filtering the performance achieved for the baseband ADC is shown to be sufficient. However, for the direct RF ADC the dynamic range and linearity requirements cannot be fully satisfied. The presented work can be considered a step ahead toward a successful implementation of the true SDR in the future.
|
|
| 4. |
- Qazi, Fahad, et al.
(författare)
-
A/D Conversion for Software Defined Radio
- 2010
-
Ingår i: Proceedings of the GigaHerz Symposium 2010. - Karlsruhe : Karlsruhe Institute of Technology. ; , s. 36-36, s. 70-76
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)
|
|
| 5. |
|
|
| 6. |
|
|
| 7. |
- Sundström, Timmy, et al.
(författare)
-
A 2.4 GS/s, 4.9 ENOB at Nyquist, single-channel pipeline ADC in 65nm CMOS
- 2010
-
Ingår i: IEEE European Solid-State Circuits Conference. - Seville : IEEE. - 9781424466627 ; , s. 370-373
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a high-speed single channel pipeline analog-to-digital converter sampling at 2.4 GS/s which, to the authors' best knowledge, is the fastest reported for pipeline converters. The use of a time-borrowing clocking scheme eliminates the comparator latency from the critical path and together with the use of fast open-loop current-mode amplifiers the high sample rate is achieved. Implemented in a 65nm general purpose CMOS technology the effective number of bits is above 4.7 in the Nyquist band, being 5.4 and 4.9 at DC and Nyquist respectively. This shows that very fast pipeline ADCs are possible to implement as key building blocks in interleaved structures.
|
|
| 8. |
- Sundström, Timmy, et al.
(författare)
-
A 2.4 GS/s, Single-channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS
- 2011
-
Ingår i: IEEE Journal of Solid-State Circuits. - : IEEE. - 0018-9200 .- 1558-173X. ; 46:7, s. 1575-1584
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample-rate is achieved through the use of fast openloop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.
|
|
| 9. |
- Sundström, Timmy, 1981-, et al.
(författare)
-
A 2.5-GS/s 30-mW 4-bit flash ADC in 90nm CMOS
- 2008
-
Ingår i: NORCHIP. - : IEEE. - 9781424424924 ; , s. 264-267
-
Konferensbidrag (refereegranskat)abstract
- A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS, avoids traditional power, speed and accuracy trade-offs by using comparator redundancy with power-gating capabilities. Redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators. Measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 gate-able comparators, the ADC achieves 4.0 effective number of bits.
|
|
| 10. |
- Sundström, Timmy, 1981-, et al.
(författare)
-
A 4-bit 2.5-GS/s 30-mW Flash ADC in 90nm CMOS
- 2009
-
Ingår i: Swedish System on Chip Conference, SSoCC, Arild, May 4-5. - Lunds universitet.
-
Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A 2.5 GS/s flash ADC, fabricated in 90nm CMOS,avoids traditional power, speed and accuracy trade-offs by usingcomparator redundancy with power-gating capabilities.Redundancy removes the need to control comparator offsets,allowing the large process-variation induced mismatch of smalldevices in nanometer technologies. This enables the use of smallsized,ultra-low-power comparators. Measurement results showthat the ADC dissipates 30 mW at 1.2 V. With 63 gate-ablecomparators, the ADC achieves 4.0 effective number of bits.
|
|
