| 1. |
- Alam, Ashraful, et al.
(author)
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Parallelization of the Estimation Algorithm of the 3D Structure Tensor
- 2012
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In: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012. - Piscataway, N.J. : IEEE Press. - 9781467329194 - 9781467329217
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Conference paper (peer-reviewed)abstract
- The three dimensional structure tensor algorithm (3D-STA) is often used in image processing applications to compute the optical flow or to detect local 3D structures and their directions. This algorithm is computationally expensive due to many computations that are required to calculate the gradient, the tensor, and to smooth every pixel of the image frames. Therefore, it is important to parallelize the implementation to achieve high performance. In this paper we present two parallel implementations of 3D-STA; namely moderately parallelized and highly parallelized implementation, on a massively parallel reconfigurable array. Finally, we evaluate the performance of the generated code and results are compared with another optical flow implementation. The throughput achieved by the moderately parallelized implementation is approximately half of the throughput of the Optical flow implementation, whereas the highly parallelized implementation results in a 2x gain in throughput as compared to the optical flow implementation. © 2012 IEEE.
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| 2. |
- Bengtsson, Lars, 1958-, et al.
(author)
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A high-performance embedded massively parallel processing system
- 1994
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In: Proceedings of the First International Conference on Massively Parallel Computing Systems (MPCS) The Challenges of General-Purpose and Special-Purpose Computing. - Piscataway, N.J. : IEEE. - 0818663227 - 9780818663222 ; , s. 201-206
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Conference paper (peer-reviewed)abstract
- A need to apply the massively parallel computing paradigm in embedded real-time systems is foreseen. Such applications put new demands on massively parallel systems, different from those of general purpose computing. For example, time determinism is more important than maximal throughput, physical distribution is often required, size, power, and I/O are important, and interactive development tools are needed. The paper describes an architecture for high-performance, embedded, massively parallel processing, featuring a large number of nodes physically distributed over a large area. A typical node has thousands of processing elements (PEs) organized in SIMD mode and is the size of the palm of a hand, Intermodule communication over a scalable optical network is described. A combination of wavelength division multiplexing (WDM) and time division multiplexing (TDM) is used. © 1994 IEEE.
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| 3. |
- Bengtsson, Lars, 1958-, et al.
(author)
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A processor array module for distributed, massively parallel, embedded computing
- 1993
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In: Microprocessing and Microprogramming. - Amsterdam : Elsevier. - 0165-6074. ; 38:1-5, s. 529-537
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Journal article (peer-reviewed)abstract
- With the increased degree of miniaturization resulting from the use of modem VLSI technology and the high communication bandwidth available through optical connections, it is now possible to build massively parallel computers based on distributed modules which can be embedded in advanced industrial products. Examples of such future possibilities are ''action-oriented systems'', in which a network of highly parallel modules perform a multitude of tasks related to perception, cognition, and action. The paper discusses questions of architecture on the level of modules and inter-module communication and gives concrete architectural solutions which meet the demands of typical, advanced industrial real-time applications. The interface between the processors arrays and the all-optical communication network is described in some detail. Implementation issues specifically related to the demand for miniaturization are discussed.
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| 4. |
- Bengtsson, Lars, 1958-, et al.
(author)
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Brains for Autonomous Robots : Hardware and Surgery Tools
- 1994
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In: Proceedings of PerAc '94. From Perception to Action. - Los Alamitos : IEEE. - 0818664827 - 9780818664823 ; , s. 436-439
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Conference paper (peer-reviewed)abstract
- This paper presents a hardware architecture and a software tool needed for future autonomous robots. Specific attention is given to the execution of artificial neural networks and to the need for a good inspection and visualization tool when developing this kind of systems. Achievable performance using state-of-the-art technology is estimated and module miniaturization issues are discussed. © 1994 IEEE.
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| 5. |
- Bengtsson, Lars, 1958-, et al.
(author)
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REMAP massively parallel computer platform for neural computations
- 1997
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In: Proceedings of the Third International Conference on Microelectronics for Neural Networks (MicroNeuro’93). ; , s. 47-62
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Conference paper (peer-reviewed)abstract
- The REMAP project addresses questions related to the use of massively parallel, distributed computing in embedded systems. Of specific interest is the execution of artificial neural network algorithms on multiple, cooperating processor arrays. This paper concentrates on the recently finished, and currently used, processor array prototype, REMAP-β, of SIMD (Single Instruction stream, Multiple Data streams) type. The architecture and implementation of the computer is described, both its overall structure and its constituent parts. Following this comes a discussion of its use as an architecture laboratory, which stems from the fact that it is implemented using FPGA (Field Programmable Gate Array) circuits. As an architecture laboratory the prototype can be used to implement and evaluate, e.g., various Processing Element (PE) designs. A couple of examples of PE architectures, including one with floating-point support, are given. The mapping of important neural network algorithms on processor arrays of this kind is shown, and possible tuning of the architecture to meet specific processing demands is discussed. Performance figures are given as well as implications for future VLSI implementations of the array.
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| 6. |
- Bilstrup, Urban, 1971-, et al.
(author)
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Knowledge Horizon - Dynamic limitations in a wireless ad hoc network
- 2003
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In: SNCNW 2003 Swedish National Computer Networking Workshop 2003 on-line proceedings. ; , s. 1-3
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Conference paper (peer-reviewed)abstract
- In this paper we investigate the impact of node mobility in a wireless ad hoc network (WAHN). Especially we investigate the possibility to provide guaranteed services in a WAHN, i.e., the network topology predictability. We combine link expiration time (LET) estimation with information propagation speed (IPS) in a time-space diagram and as result an operation area is revealed. The result gives that a WAHN, where the nodes are mobile, has a knowledge horizon (KH), the distance of which is dependent on the mobility of the nodes. Beyond the KH, knowledge about the network state is impossible to achieve. Thus, we can not predict long distance network topology state when the node mobility is high.
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| 7. |
- Boström, Ola, 1963, et al.
(author)
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A new neck injury criterion candidate-based on injury findings in the cervical spinal ganglia after experimental neck extension trauma
- 1996
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In: PROCEEDINGS OF THE 1996 INTERNATIONAL IRCOBI CONFERENCE ON THE BIOMECHANICS OF IMPACT, SEPTEMBER 11-13, DUBLIN, IRELAND. ; , s. 123-136
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Conference paper (peer-reviewed)abstract
- In this study a mathematical model, based on Navier Stokes equations, was developed and validated against experimental data. This model predicts the pressure changes in the spinal canal as a function of the volume change inside the canal during neck bending in the x-z (sagittal) plane. Another aim of the study was to investigate pressure phenomena and ganglion injuries at static neck extension loading and dynamic neck extension trauma with a head-restraint present. Experiments on pigs were conducted. Preliminary results indicate that ganglion injuries, as well as pressure transients inside the spinal canal, seem to correlate to the phase shift when the neck passes an s-shape (or maximal retraction) during the rearward motion of the head. That is, when the upper neck quickly changes from a flexion to an extension shape. Static loading of the neck resulted in no signs of injuries to the ganglia. A possible candidate for a neck injury criterion is presented, based on the relative acceleration between the top and the bottom of the cervical spine. A tolerance level based on the pig tests is also discussed.
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| 8. |
- Boström, Ola, 1963, et al.
(author)
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Prediction of neck injuries in rear impacts based on accident data and simulations
- 1997
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In: PROCEEDINGS OF THE 1997 INTERNATIONAL IRCOBI CONFERENCE ON THE BIOMECHANICS OF IMPACT. ; , s. 251-264
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Conference paper (peer-reviewed)abstract
- Whiplash associated disorders, occurring in car accidents, are an increasing problem worldwide. According to real-life data from police records, the struck car's velocity change (delta V) and occupant gender are two of the most important factors related to Abbreviated Injury Scale (AIS) 1 neck injuries. In this study, a new rear-impact ranking of cars based on 4432 police reported accidents is presented. The ranking concerns the relative neck injury risk and compensates for the influences of car weight and gender. Moreover, some important factors influencing the risk of AIS 1 neck injury are proposed. These include: the stiffness, damping and yielding characteristics of the seat back, the muscle response of the occupant, and the delta V of the struck car and acceleration pulse. Using a mathematical model it is shown that the influence from these factors can be explained by a recently proposed neck injury criterion (NIC). This criterion is based on the neck motion at the passage of full neck retraction. The NIC, based on a number of volunteer tests, is analysed and validated. The consequence of injury outcome of an observed overall seat back stiffening is also discussed. In conclusion, for delta V below 20 km/h, real-life data show that the geometry of the head restraint is of minor importance. A seat back with low yielding limit or soft performance may be preferable. Moreover, the new NIC seems to be a good predictor of real-life neck injuries.
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| 9. |
- Essayas, Gebrewahid, 1984-, et al.
(author)
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Realizing Efficient Execution of Dataflow Actors on Manycores
- 2014
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In: 2014 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC 2014). - Los Alamitos, CA : IEEE Computer Society. ; , s. 321-328, s. 321-328
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Conference paper (peer-reviewed)abstract
- Embedded DSP computing is currently shifting towards manycore architectures in order to cope with the ever growing computational demands. Actor based dataflow languages are being considered as a programming model. In this paper we present a code generator for CAL, one such dataflow language. We propose to use a compilation tool with two intermediate representations. We start from a machine model of the actors that provides an ordering for testing of conditions and firing of actions. We then generate an Action Execution Intermediate Representation that is closer to a sequential imperative language like C and Java. We describe our two intermediate representations and show the feasibility and portability of our approach by compiling a CAL implementation of the Two-Dimensional Inverse Discrete Cosine Transform on a general purpose processor, on the Epiphany manycore architecture and on the Ambric massively parallel processor array.
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| 10. |
- Forsberg, Håkan, 1969-, et al.
(author)
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Opportunities for Optical Planar Interconnection Technology in Terabit Switches
- 2003
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In: Proceedings of the IASTED International Conference on Wireless and Optical Communications, July 2-4, 2003, Banff, Canada. - Anaheim; Calgary : ACTA Press. - 0889863741 - 9780889863743 ; , s. 155-164
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Conference paper (peer-reviewed)abstract
- To keep up with the explosive growth of world-wide network traffic, large-capacity switches, with switching capacities in excess of several terabits per second, are becoming an essential part of the future. To realize such switches, new architecture concepts must be considered. In this paper, we discuss a technology for terabit switches that combines the advantage of using optical communication in all three spatial dimensions and the benefits of using surface mounted optoelectronic as well as electronic chips. We present three different types of packet-based switch fabrics, all based on the optical planar interconnection technology. We then discuss these in terms of capacity, scalability, and physical size. All three implementations have a single switch plane cross sectional bandwidth exceeding 5 Tbps.
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