| 1. |
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- 2019
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Tidskriftsartikel (refereegranskat)
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| 2. |
- Dawji, Yunus, et al.
(författare)
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A 65-nm CMOS Low-Power Front-End for 3rd Generation DNA Sequencing
- 2019
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Ingår i: 2019 IEEE Sensors, SENSORS 2019 - Conference Proceedings. - 1930-0395 .- 2168-9229. - 9781728116341 ; 2019-October
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Konferensbidrag (refereegranskat)abstract
- A continuous-time, 65-nm CMOS, front-end for processing DNA sequencing measurements from biological nanopore sensors is presented. The measured design has an input referred noise floor of 8.5\;{\text{fA}}/\sqrt {{\text{Hz}}} for 100 pA DC current while consuming 10X less power. The chip also consists of an integrated ADC.
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| 3. |
- Diaz, Isael, et al.
(författare)
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A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS
- 2015
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Ingår i: 2015 IEEE International Symposium on Circuits and Systems (ISCAS). - 9781479983919
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Konferensbidrag (refereegranskat)abstract
- Correct estimation of symbol timing, Carrier Frequency Offset (CFO), and Signal-to-Noise Ratio (SNR) is crucial in Orthogonal Frequency Division Multiplexing (OFDM) communication. Typically, high estimation accuracy is desired, but often comes with increased complexity. Which has a direct repercussion in energy consumption. In this article, an architecture based on Sign-Bit estimation with low complexity, and hence low power dissipation, is presented. The architecture, is capable of estimating the afore-mentioned parameters in virtually any OFDM standard. The proof of concept has been fabricated in 65 nm CMOS technology with low-power high-VT cells. Measurements performed with supply voltage of 1.2V. resulted in a power dissipation of 350 μW, 6 times smaller to that of an equivalent 8-bit architecture, and the lowest power density reported in literature.
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| 4. |
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| 5. |
- Felding, Henrik, et al.
(författare)
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A three bit second order audio band delta sigma modulator with 98.2dB SQNR
- 2016
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Ingår i: 2016 International Symposium on Integrated Circuits, ISIC 2016. - 9781467390194
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Konferensbidrag (refereegranskat)abstract
- A three bit second order delta sigma modulator for audio applications implemented in 130nm CMOS technology is presented. The modulator features two integrators, a flash quantizer and two current steering DACs. In order to minimize the effect of delays in the DACs, excessive loop delay (ELD) compensation is utilized. Using an oversampling ratio (OSR) of 80, the design consumes 2.8mW and achieves a simulated signal to quantization noise ratio (SQNR) of 98.2dB. The chip area is minimized by decreasing the number of digital to analog converters (DACs) by using the concept of partial integration. The compact design occupies an active core area of 630μm × 600μm.
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| 6. |
- Karrari, Hamid, et al.
(författare)
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A 1.4 GS/s TI Pipelined-SAR analog-to-digital converter in 22-nm FDSOI CMOS
- 2023
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Ingår i: 2023 IEEE Nordic Circuits and Systems Conference, NorCAS 2023 - Proceedings. - 9798350337570
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Konferensbidrag (refereegranskat)abstract
- This paper presents a 4-channel time-interleaved (TI) analog-to-digital converter (ADC), where each channel is comprised of a two-stage pipelined asynchronous successive-approximation (ASAR) sub-ADC. The ADC employs two samplers to alleviate the problem of timing skew on the sub-sampler when distributing the clock to the TI channels. To further increase the speed of the ADC, the reset switch in the capacitive digital-to-analog converter of each sub-ADC is also boot-strapped. The ADC is implemented in a 22-nm CMOS FDSOI technology. With a sampling rate of 1.4 GS/s, measurements show that the ADC achieves an SNDR of 50 dB with a low-frequency input. The SNDR drops by only 1.5 dB at Nyquist. Powered by a 0.8 V supply, the total power consumption of the ADC is 37.5 mW, while the ADC core consumes 19.3 mW.
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| 7. |
- Karrari, Hamid, et al.
(författare)
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A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
- 2024
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Ingår i: IEEE Access. - 2169-3536. ; 12, s. 44115-44124
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Tidskriftsartikel (refereegranskat)abstract
- A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstrapped sampler in front of the four channels is employed. The reset switch in the capacitive digital-to-analog converter (CDAC) of each channel is also bootstrapped to enhance the speed and linearity. A prototype ADC has been designed and implemented in a 22-nm FDSOI CMOS technology, with a core occupation area of 0.43 mm2. Measurements show that the ADC achieves a signal-to-noise-and-distortion ratio of 50dB with a low-frequency input, and of 48.5 dB at Nyquist. The total power consumption is 37.5 mW; the core ADC consumes 19.3 mW from a 0.8V supply. With a 1.4 GS/s sampling rate and input at Nyquist, the ADC achieves a Walden's figure of merit of 114 fJ/conversion.
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| 8. |
- Karrari, Hamid, et al.
(författare)
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A High-Speed Comparator Using a New Regeneration Latch
- 2023
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Ingår i: 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023. - 9798350302103 ; , s. 624-628
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Konferensbidrag (refereegranskat)abstract
- This paper presents a high-speed comparator which employs a novel regeneration latch to enhance the comparison process. The regeneration stage employs an innovative mechanism that reduces the RC constant at the output while avoiding static power consumption. Furthermore, the proposed comparator is capable of operating seamlessly with a rail-to-rail input common-mode voltage. This is made possible by utilizing two preamplifiers working in parallel. To partially cancel out kickback noise, the proposed comparator also benefits from an intrinsic neutralization technique. The design was simulated in a 22-nm FD-SOI CMOS technology with a supply voltage of 0.8 V showing that the proposed comparator achieves a 17% decrease in delay compared to the fastest conventional topology simulated in this paper, while consuming the same amount of power.
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| 9. |
- Karrari, Hamid, et al.
(författare)
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A Technique to Increase the Linearity of the Bootstrapped Switch
- 2023
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Ingår i: 2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023. - 9798350302103 ; , s. 1001-1004
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Konferensbidrag (refereegranskat)abstract
- We present a detailed investigation into a source of distortion that affects the classic bootstrapped switch. Our analysis reveals that the transition phase between track mode and hold mode is a critical factor in causing the distortion. To address this issue, we propose a novel technique that effectively mitigates the problem. Our results, based on simulations conducted using a 22-nm FDSOI CMOS process, show an improvement of at least 4 dB in the signal-to-distortion ratio, with only a minor reduction in signal bandwidth. Importantly, the increase in SDR is achieved with a minimum cost in terms of power consumption and area occupation.
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| 10. |
- Tan, Siyu, et al.
(författare)
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A 10-bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration
- 2020
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Ingår i: 2020 IEEE International Symposium on Circuits and Systems (ISCAS). - 9781728133218 - 9781728133201
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Konferensbidrag (refereegranskat)abstract
- This paper presents a 10-bit SAR ADC with a sampling rate of 200 MS/s. To reduce area and power consumption, the ADC adopts a split-capacitor DAC, where the gain error is estimated and subsequently removed by means of a PRBS signal injected into the DAC and detected at the ADC output. The ADC has been designed and fabricated in a 22nm FD-SOI CMOS process, and achieves an SNDR of 48.7 dB and an SFDR of 66.7 dB for input frequencies up to the sampling frequency, with a power consumption of 4.3mW and an FoM of 152 dB.
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