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- Berkeman, Anders, et al.
(författare)
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A low logic depth complex multiplier
- 1998
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Ingår i: ; , s. 204-207
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Konferensbidrag (refereegranskat)abstract
- A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.
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| 5. |
- Berkeman, Anders, et al.
(författare)
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A low logic depth complex multiplier using distributed arithmetic
- 2000
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 35:4, s. 656-659
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Tidskriftsartikel (refereegranskat)abstract
- A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-μm process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions
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| 7. |
- Berkeman, Anders, et al.
(författare)
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Implementation Issues for acoustic echo cancellers
- 1999
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Ingår i: [Host publication title missing]. - 0780354915 ; , s. 97-100
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Konferensbidrag (refereegranskat)abstract
- The high computational complexity of acoustic echo cancellation algorithms requires application specific implementations to sustain real time signal processing with affordable power consumption. This is especially true for systems where a delayless approach is considered important, e.g. wireless communication systems. The proposed paper presents architectural considerations to reach a feasible hardware solution.
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- He, Shousheng, et al.
(författare)
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A new approach to pipeline FFT processor
- 1996
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Ingår i: [Host publication title missing]. - 0818672552 ; , s. 766-770
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Konferensbidrag (refereegranskat)abstract
- A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL.
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- He, Shousheng, et al.
(författare)
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Design and implementation of a 1024-point pipeline FFT processor
- 1998
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Ingår i: [Host publication title missing]. - 0780342925 ; , s. 131-134
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Konferensbidrag (refereegranskat)abstract
- The design and implementation of a 1024-point pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radix-22 algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in 0.5 μm CMOS technology and takes an area of 40 mm2. With 3.3 V power supply, it can compute 2n , n=0, 1, ..., 10 complex point forward and inverse FFT in real time with up to 30 MHz sampling frequency. The SQNR is above 50 dB for white noise input.
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- He, Shousheng, et al.
(författare)
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Designing pipeline FFT processor for OFDM (de)modulation
- 1998
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Ingår i: [Host publication title missing]. - 0780349008 ; , s. 257-262
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Konferensbidrag (refereegranskat)abstract
- The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2i algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point processing. A new complex multiplier based on distributed arithmetic further enhanced the area/power efficiency of the design. A single-chip processor for 1 K complex point FFT transform is used to demonstrate the design issues under consideration.
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