| 1. |
- Andersson, Niklas, et al.
(författare)
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Models and Implementation of a Dynamic Element Matching DAC
- 2003
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Ingår i: Analog Integrated Circuits and Signal Processing. - Netherlands : Springer. - 0925-1030 .- 1573-1979. ; 34:1, s. 7-16
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Tidskriftsartikel (refereegranskat)abstract
- The dynamic element matching (DEM) techniques for digital-to-analog converters (DACs) has been suggested as a promising method to improve matching between the DAC''s reference levels. However, no work has so far taken the dynamic effects that limit the performance for higher frequenciesinto account. In this paper we present a model describing the dynamic properties of a DEM DAC and compare the simulated results with measurements of a 14-bit current-steering DEM DAC implemented in a 0.35-μm CMOS process. The measured data agrees well with the results predicted by the used model. It is also shown that the DEM technique does not necessarily increase the performance of a DAC when dynamic errors are dominating the achievable performance.
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| 2. |
- Andersson, Ola, et al.
(författare)
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A 14-Bit dual current-steering DAC
- 2003
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Ingår i: Proc. Swedish System-on-Chip Conf., SSoCC'03.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.
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| 3. |
- Andersson, Ola, et al.
(författare)
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A differential DAC architecture with variable common-mode level
- 2002
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Ingår i: Proc. 2002 IEEE Int. Symp. on Circuits and Systems, ISCAS'02. - 0780374487 ; , s. I-113-I-116
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Konferensbidrag (refereegranskat)abstract
- A differential current-steering digital-to-analog converter (DAC) architecture allowing the common-mode level of the input signal to be varied is presented. Simulation results with models of different DAC nonlinearities indicate that the proposed architecture has a potential of improving the linearity of the converters.
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| 4. |
- Andersson, Ola, et al.
(författare)
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A method of segmenting digital-to-analog converters
- 2003
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Ingår i: Proc. IEEE Southwest Symposium on Mixed-Signal Design, SSMSD'03. - 0780377788 ; , s. 32-37
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Konferensbidrag (refereegranskat)abstract
- Segmented architectures are often used in digital-to-analog converters (DACs). Here we propose a DAC structure based on recursive decomposition of an N-bit binary DAC into two (N-1) bit DACs and one 1 bit DAC. A DAC model that includes matching errors has been simulated. The simulation results indicate that by using four layers of decomposition it is possible to achieve similar performance as when using seven bits of traditional segmentation.
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| 5. |
- Andersson, Ola, 1976-, et al.
(författare)
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A parameterized cell-based design approach for digital-to-analog converters
- 2004
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Ingår i: Proc. IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04. - 0769521827 ; , s. 225-228
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Konferensbidrag (refereegranskat)abstract
- Due to the lack of proper design automation tools, designers are often forced to use full-custom design methodologies when designing analog and mixed-signal circuits. In this work, we discuss a design methodology based on parameterized cells intended for efficient design. The methodology is illustrated with the design of a 12-bit configurable current-steering DAC. Because the cells are parameterized, their layout must be described in a generalized way, resulting in a longer design time compared with a manual layout of a fixed circuit. However, the parameterized approach simplifies iteration of the layout process and block reuse.
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| 6. |
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| 7. |
- Andersson, Ola, 1976-, et al.
(författare)
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A yield-enhancement strategy for binary-weighted DACs
- 2005
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Ingår i: Proc. European Conf. Circuit Theory and Design 2005, ECCTD'05. - 0780390660 ; , s. 55-58
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Konferensbidrag (refereegranskat)abstract
- One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.
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| 8. |
- Andersson, Ola, et al.
(författare)
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Combining DACs for improved performance
- 2002
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Ingår i: Proc. 4th IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and their Applications, ADDA'02.
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Konferensbidrag (refereegranskat)abstract
- This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.
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| 9. |
- Andersson, Ola, 1976-, et al.
(författare)
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Dynamic element matching in decomposed digital-to-analog converters
- 2004
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Ingår i: Proc. IEEE NORCHIP'04. - Denmark : TechnoData A/S. - 0780385101 ; , s. 187-190
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Konferensbidrag (refereegranskat)abstract
- A dynamic element matching (DEM) technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed converter architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90% yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.
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| 10. |
- Andersson, Ola, et al.
(författare)
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Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters
- 2005
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Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - Piscataway : IEEE. - 1549-8328. ; 52:11, s. 2265-2275
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Tidskriftsartikel (refereegranskat)abstract
- The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.
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