| 1. |
- Liu, Lizheng, et al.
(författare)
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A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network
- 2020
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Ingår i: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- The Bayesian Confidence Propagation Neural Network (BCPNN) has been applied in higher level of cognitive intelligence (e.g. working memory, associative memory). However, in the spike-based version of this learning rule the pre-, postsynaptic and coincident activity is traced in three low-passfiltering stages, the calculation processes of weight update are very computationally intensive. In this paper, a hardware architecture of the updating process for lazy update mode is proposed for updating 8 local synaptic state variables. The parallelism by decomposing the calculation steps of formulas based on the inherent data dependencies is optimized. The FPGA-based hardware accelerator of BCPNN is designed and implemented. The experimental results show the updating process on FPGA can be accomplished within 110 ns with a clock frequency of 200 MHz, the updating speed is greatly enhanced compared with the CPU test. The trade-off between performance, accuracy and resources on dedicated hardware is evaluated, and the impact of the module reuse on resource consumption and computing performance is evaluated.
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| 2. |
- Wang, Deyu, et al.
(författare)
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FPGA-Based HPC for Associative Memory System
- 2024
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Ingår i: 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 52-57
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Konferensbidrag (refereegranskat)abstract
- Associative memory plays a crucial role in the cognitive capabilities of the human brain. The Bayesian Confidence Propagation Neural Network (BCPNN) is a cortex model capable of emulating brain-like cognitive capabilities, particularly associative memory. However, the existing GPU-based approach for BCPNN simulations faces challenges in terms of time overhead and power efficiency. In this paper, we propose a novel FPGA-based high performance computing (HPC) design for the BCPNN-based associative memory system. Our design endeavors to maximize the spatial and timing utilization of FPGA while adhering to the constraints of the available hardware resources. By incorporating optimization techniques including shared parallel computing units, hybrid-precision computing for a hybrid update mechanism, and the globally asynchronous and locally synchronous (GALS) strategy, we achieve a maximum network size of 150x10 and a peak working frequency of 100 MHz for the BCPNN-based associative memory system on the Xilinx Alveo U200 Card. The tradeoff between performance and hardware overhead of the design is explored and evaluated. Compared with the GPU counterpart, the FPGA-based implementation demonstrates significant improvements in both performance and energy efficiency, achieving a maximum latency reduction of 33.25x, and a power reduction of over 6.9x, all while maintaining the same network configuration.
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| 3. |
- Wang, Deyu, et al.
(författare)
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Memristor-Based In-Circuit Computation for Trace-Based STDP
- 2022
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Ingår i: 2022 Ieee International Conference On Artificial Intelligence Circuits And Systems (Aicas 2022). - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Recently, memristors have been widely used to implement Spiking Neural Networks (SNNs), which is promising in edge computing scenarios. However, most memristor-based SNN implementations adopt simplified spike-timing-dependent plasticity (STDP) for the online learning process. It is challenging for memristor-based implementations to support the trace-based STDP learning rules that have been widely used in neuromorphic applications. This paper proposed a versatile memristor-based architecture to implement the synaptic-level trace-based STDP learning rules. Especially, the similarity between synaptic trace dynamics and the memristor nonlinearity is explored and exploited to emulate the trace variables of trace-based STDP. As two typical trace-based STDP learning rules, the pairwise STDP and the triplet STDP, are simulated on two typical nonlinear bipolar memristor devices. The simulation results show that the behavior of physical memristor devices can be well estimated (below 6% in terms of the relative root-mean-square error), and the memristor-based in-circuit computation for trace-based STDP learning rules can achieve a high correlation coefficient over 98%.
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| 4. |
- Horn, Agnes-Marie, et al.
(författare)
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ISSC Committee III.2 - Fatigue and fracture
- 2014
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Ingår i: Proceedings of The 18th International Ship and Offshore Structures Congress (ISSC 2012). ; 3, s. 129-151
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Konferensbidrag (refereegranskat)abstract
- (COMMITTEE MANDATE) Concern for crack initiation and growth under cyclic loading as well as unstable crack propagation and tearing in ship and offshore structures. Due attention shall be paid to practical application and statistical description of fracture control methods in design, fabrication and service. Consideration is to be given to the suitability and uncertainty of physical models.
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| 5. |
- Kottwitz, Matthew, et al.
(författare)
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Local Structure and Electronic State of Atomically Dispersed Pt Supported on Nanosized CeO2
- 2019
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Ingår i: ACS Catalysis. - : AMER CHEMICAL SOC. - 2155-5435. ; 9:9, s. 8738-8748
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Tidskriftsartikel (refereegranskat)abstract
- Single atom catalysts (SACs) have shown high activity and selectivity in a growing number of chemical reactions. Many efforts aimed at unveiling the structure-property relationships underpinning these activities and developing synthesis methods for obtaining SACs with the desired structures are hindered by the paucity of experimental methods capable of probing the attributes of local structure, electronic properties, and interaction with support-features that comprise key descriptors of their activity. In this work, we describe a combination of experimental and theoretical approaches that include photon and electron spectroscopy, scattering, and imaging methods, linked by density functional theory calculations, for providing detailed and comprehensive information on the atomic structure and electronic properties of SACs. This characterization toolbox is demonstrated here using a model single atom Pt/CeO2 catalyst prepared via a sol-gel-based synthesis method. Isolated Pt atoms together with extra oxygen atoms passivate the (100) surface of nanosized ceria. A detailed picture of the local structure of Pt nearest environment emerges from this work involving the bonding of isolated Pt2+ ions at the hollow sites of perturbed (100) surface planes of the CeO2 support, as well as a substantial (and heretofore unrecognized) strain within the CeO2 lattice in the immediate vicinity of the Pt centers. The detailed information on structural attributes provided by our approach is the key for understanding and improving the properties of SACs.
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| 6. |
- Wang, Deyu, et al.
(författare)
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A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning
- 2023
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Ingår i: IEEE Transactions on Biomedical Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1932-4545 .- 1940-9990. ; 17:5, s. 1153-1165
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Tidskriftsartikel (refereegranskat)abstract
- The memristor has been extensively used to facilitate the synaptic online learning of brain-inspired spiking neural networks (SNNs). However, the current memristor-based work can not support the widely used yet sophisticated trace-based learning rules, including the trace-based Spike-Timing-Dependent Plasticity (STDP) and the Bayesian Confidence Propagation Neural Network (BCPNN) learning rules. This paper proposes a learning engine to implement trace-based online learning, consisting of memristor-based blocks and analog computing blocks. The memristor is used to mimic the synaptic trace dynamics by exploiting the nonlinear physical property of the device. The analog computing blocks are used for the addition, multiplication, logarithmic and integral operations. By organizing these building blocks, a reconfigurable learning engine is architected and realized to simulate the STDP and BCPNN online learning rules, using memristors and 180 nm analog CMOS technology. The results show that the proposed learning engine can achieve energy consumption of 10.61 pJ and 51.49 pJ per synaptic update for the STDP and BCPNN learning rules, respectively, with a 147.03× and 93.61× reduction compared to the 180 nm ASIC counterparts, and also a 9.39× and 5.63× reduction compared to the 40 nm ASIC counterparts. Compared with the state-of-the-art work of Loihi and eBrainII, the learning engine can reduce the energy per synaptic update by 11.31× and 13.13× for trace-based STDP and BCPNN learning rules, respectively.
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| 7. |
- Wang, Deyu, et al.
(författare)
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Mapping the BCPNN Learning Rule to a Memristor Model
- 2021
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Ingår i: Frontiers in Neuroscience. - : Frontiers Media SA. - 1662-4548 .- 1662-453X. ; 15
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Tidskriftsartikel (refereegranskat)abstract
- The Bayesian Confidence Propagation Neural Network (BCPNN) has been implemented in a way that allows mapping to neural and synaptic processes in the human cortexandhas been used extensively in detailed spiking models of cortical associative memory function and recently also for machine learning applications. In conventional digital implementations of BCPNN, the von Neumann bottleneck is a major challenge with synaptic storage and access to it as the dominant cost. The memristor is a non-volatile device ideal for artificial synapses that fuses computation and storage and thus fundamentally overcomes the von Neumann bottleneck. While the implementation of other neural networks like Spiking Neural Network (SNN) and even Convolutional Neural Network (CNN) on memristor has been studied, the implementation of BCPNN has not. In this paper, the BCPNN learning rule is mapped to a memristor model and implemented with a memristor-based architecture. The implementation of the BCPNN learning rule is a mixed-signal design with the main computation and storage happening in the analog domain. In particular, the nonlinear dopant drift phenomenon of the memristor is exploited to simulate the exponential decay of the synaptic state variables in the BCPNN learning rule. The consistency between the memristor-based solution and the BCPNN learning rule is simulated and verified in Matlab, with a correlation coefficient as high as 0.99. The analog circuit is designed and implemented in the SPICE simulation environment, demonstrating a good emulation effect for the BCPNN learning rule with a correlation coefficient as high as 0.98. This work focuses on demonstrating the feasibility of mapping the BCPNN learning rule to in-circuit computation in memristor. The feasibility of the memristor-based implementation is evaluated and validated in the paper, to pave the way for a more efficient BCPNN implementation, toward a real-time brain emulation engine.
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| 8. |
- Wang, Zhen, et al.
(författare)
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Copper-Plated Paper for High-Performance Lithium-Ion Batteries
- 2018
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Ingår i: Small. - : Wiley-VCH Verlagsgesellschaft. - 1613-6810 .- 1613-6829. ; 14:48
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Tidskriftsartikel (refereegranskat)abstract
- Paper is emerging as a promising flexible, high surface-area substrate for various new applications such as printed electronics, energy storage, and paper-based diagnostics. Many applications, however, require paper that reaches metallic conductivity levels, ideally at low cost. Here, an aqueous electroless copper-plating method is presented, which forms a conducting thin film of fused copper nanoparticles on the surface of the cellulose fibers. This paper can be used as a current collector for anodes of lithium-ion batteries. Owing to the porous structure and the large surface area of cellulose fibers, the copper-plated paper-based half-cell of the lithium-ion battery exhibits excellent rate performance and cycling stability, and even outperforms commercially available planar copper foil-based anode at ultra-high charge/discharge rates of 100 C and 200 C. This mechanically robust metallic-paper composite has promising applications as the current collector for light-weight, flexible, and foldable paper-based 3D Li-ion battery anodes.
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| 9. |
- Wu, Hanyan, et al.
(författare)
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Stable organic electrochemical neurons based on p-type and n-type ladder polymers
- 2023
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Ingår i: Materials Horizons. - : ROYAL SOC CHEMISTRY. - 2051-6347 .- 2051-6355. ; :10, s. 4213-4223
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Tidskriftsartikel (refereegranskat)abstract
- Organic electrochemical transistors (OECTs) are a rapidly advancing technology that plays a crucial role in the development of next-generation bioelectronic devices. Recent advances in p-type/n-type organic mixed ionic-electronic conductors (OMIECs) have enabled power-efficient complementary OECT technologies for various applications, such as chemical/biological sensing, large-scale logic gates, and neuromorphic computing. However, ensuring long-term operational stability remains a significant challenge that hinders their widespread adoption. While p-type OMIECs are generally more stable than n-type OMIECs, they still face limitations, especially during prolonged operations. Here, we demonstrate that simple methylation of the pyrrole-benzothiazine-based (PBBT) ladder polymer backbone results in stable and high-performance p-type OECTs. The methylated PBBT (PBBT-Me) exhibits a 25-fold increase in OECT mobility and an impressive 36-fold increase in & mu;C* (mobility x volumetric capacitance) compared to the non-methylated PBBT-H polymer. Combining the newly developed PBBT-Me with the ladder n-type poly(benzimidazobenzophenanthroline) (BBL), we developed complementary inverters with a record-high DC gain of 194 V V-1 and excellent stability. These state-of-the-art complementary inverters were used to demonstrate leaky integrate-and-fire type organic electrochemical neurons (LIF-OECNs) capable of biologically relevant firing frequencies of about 2 Hz and of operating continuously for up to 6.5 h. This achievement represents a significant improvement over previous results and holds great potential for developing stable bioelectronic circuits capable of in-sensor computing.
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| 10. |
- Xu, Jiawei, et al.
(författare)
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A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation
- 2021
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Ingår i: 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS. - : Institute of Electrical and Electronics Engineers (IEEE).
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Konferensbidrag (refereegranskat)abstract
- This paper proposes a concise window function to build a memristor model, simulating the widely-observed non-linear dopant drift phenomenon of the memristor. Exploiting the non-linearity, the memristor model is applied to the in-situ neuromorphic solution for a cortex-inspired spiking neural network (SNN), spike-based Bayesian Confidence Propagation Neural Network (BCPNN). The improved memristor model utilizing the proposed window function is able to retain the boundary effect and resolve the boundary lock and inflexibility problem, while it is simple in form that can facilitate large-scale neuromorphic model simulation. Compared with the state-of-the-art general memristor model, the proposed memristor model can achieve a 5.8x reduction of simulation time at a competitive fitting level in cortex-comparable large-scale software simulation. The evaluation results show an explicit similarity between the non-linear dopant drift phenomenon of the memristor and the BCPNN learning rule, and the memristor model is able to emulate the key traces of BCPNN with a correlation coefficient over 0.99.
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