| 1. |
- Guo (郭佳诚), Jiacheng, et al.
(författare)
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Vortex dynamics and fin-fin interactions resulting in performance enhancement in fish-like propulsion
- 2023
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Ingår i: Physical Review Fluids. - 2469-990X. ; 8:7
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Tidskriftsartikel (refereegranskat)abstract
- The leading-edge vortex (LEV) formation on the caudal fin (CF) has been identified as playing a key role in efficient lift-based thrust production of fish-like propulsion. The enhancement of the CF LEV through its interaction with vortices formed upstream due to a median fin with a distinct shape is the focus of this paper. High-speed, high-fidelity videos and particle imaging velocimetry (PIV) were obtained from rainbow trout during steady forward swimming to visualize the undulatory kinematics and two-dimensional flow behavior. Body kinematics are quantified using a traveling-wave formulation that is used to prescribe the motion of a high-fidelity three-dimensional surface model of the fish body for a computational fluid dynamics (CFD) study. The pressure field of the CFD result is compared and validated with the PIV result from the experiment. Using CFD, the vortex forming and shedding behaviors of the anal fin (AF) and their capturing and interaction with the trunk (TK) and the CF are visualized and examined. Coherent AF-bound LEVs are found to form periodically, leading to thrust production of the AF. The vortices subsequently shed from the AF are found to help stabilize and reinforce the LEV formation on the CF by aiding LEV initiation at stroke reversal and enhancing LEV during a tail stroke, which leads to enhancement of lift-based thrust production. The CF is found to shed vortex tubes (VTs) that create backward-facing jets, and the ventral-side VT and the associated backward jets are both strengthened by vortices shed by the AF. An additional benefit of the AF is found to be reduction of body drag by reducing the lateral crossflow that leads to loss of beneficial pressure gradient across the body. Through varying AF-CF spacing and AF height, we find that CF thrust enhancement and TK drag reduction due to the AF are both affected by the position and size of the AF. The position and area of the AF that led to the most hydrodynamic benefit are found to be the original, anatomically accurate position and size. In this paper, we demonstrate the important effect of vortex interaction among propulsive surfaces in fish-like propulsion.
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| 2. |
- Huang, Letian, et al.
(författare)
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A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip
- 2018
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Ingår i: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC). - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509006021 ; , s. 147-152
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Konferensbidrag (refereegranskat)abstract
- Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.
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| 3. |
- Huang, Letian, et al.
(författare)
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Non-Blocking Testing for Network-on-Chip
- 2016
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Ingår i: IEEE Transactions on Computers. - : IEEE. - 0018-9340 .- 1557-9956. ; 65:3, s. 679-692
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Tidskriftsartikel (refereegranskat)abstract
- To achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approach which could test multiple routers simultaneously at high speed without blocking or dropping packets. We first introduce a reconfigurable router architecture allowing the cores to keep their connections with the network while the routers are under test. A deadlock-free and highly adaptive routing algorithm is proposed to support reconfigurations for testing. In addition, a testing sequence is defined to allow testing multiple routers to avoid dropping of packets. A procedure is proposed to control the behavior of the affected packets during the transition of a router from the normal to the testing mode and vice versa. This approach neither interrupts the execution of applications nor has a significant impact on the execution time. Experiments with the PARSEC benchmarks on an 8x8 NoC-based chip multiprocessors show only 3 percent execution time increase with four routers simultaneously under test.
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| 4. |
- Jiang, Shuyan, et al.
(författare)
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Optimizing Dynamic Mapping Techniques for On-Line NoC Test
- 2018
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Ingår i: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). - : IEEE. - 9781509006021 ; , s. 227-232
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Konferensbidrag (refereegranskat)abstract
- With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the main goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring about the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle links are identified and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from when the application leaves the platform and a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping. This leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF, NN, CoNA, and WeNA.
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| 5. |
- Jiang, Shuyan, et al.
(författare)
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Testing aware dynamic mapping for path-centric network-on-chip test
- 2019
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Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 67, s. 134-143
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Tidskriftsartikel (refereegranskat)abstract
- With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the primary goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle paths are identified, and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from the time when the application leaves the platform to the time when a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping, which leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF(Fiexitrst Free), NN(Nearest Neighbor), CoNA(Contiguous Neighborhood Allocation), and WeNA(Weighted-based Neighborhood Allocation).
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| 6. |
- Wang, Junshi, et al.
(författare)
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Efficient Design-for-Test Approach for Networks-on-Chip
- 2019
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Ingår i: IEEE Transactions on Computers. - : IEEE Computer Society Digital Library. - 0018-9340 .- 1557-9956. ; 68:2, s. 198-213
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Tidskriftsartikel (refereegranskat)abstract
- To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.
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| 7. |
- Zhan, Junkai, et al.
(författare)
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Online Path-based Test Method for Network-on-Chip
- 2019
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Ingår i: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). - : IEEE. - 9781728103976
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Konferensbidrag (refereegranskat)abstract
- A considerable amount of routers and links remains idle after each mapping application onto the Network-on-Chip based many-core systems. Online path-based test method is a kind of self-test for these idle components. In this paper, a path-based fabric for NoC is firstly proposed. A path serves as the basic component, covering one link and its associated control logic in the routers. One possibility is to apply fault detection on the idle paths, while the other paths continue to operate normally. Moreover, this paper details the hardware implementation, targeting the stuck-at and bridging faults. It suggests a good trade-off between fault coverage, hardware overhead and test time. Experimental results show that the approach achieves 93% of the stuck-at faults in control unit and cover 100% of the stuck-at and bridging faults on the global link within 256 clock cycles.
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| 8. |
- Zhang, Wei, et al.
(författare)
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An efficient tree-topological local mesh refinement on Cartesian grids for multiple moving objects in incompressible flow
- 2023
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Ingår i: Journal of Computational Physics. - : Elsevier BV. - 0021-9991 .- 1090-2716. ; 479
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Tidskriftsartikel (refereegranskat)abstract
- This paper develops a tree-topological local mesh refinement (TLMR) method on Cartesian grids for the simulation of bio-inspired flow with multiple moving objects. The TLMR nests refinement mesh blocks of structured grids to the target regions and arrange the blocks in a tree topology. The method solves the time-dependent incompressible flow using a fractional-step method and discretizes the Navier-Stokes equation using a finite-difference formulation with an immersed boundary method to resolve the complex boundaries. When iteratively solving the discretized equations across the coarse and fine TLMR blocks, for better accuracy and faster convergence, the momentum equation is solved on all blocks simultaneously, while the Poisson equation is solved recursively from the coarsest block to the finest ones. When the refined blocks of the same block are connected, the parallel Schwarz method is used to iteratively solve both the momentum and Poisson equations. Convergence studies show that the algorithm is second-order accurate in space for both velocity and pressure, and the developed mesh refinement technique is benchmarked and demonstrated by several canonical flow problems. The TLMR enables a fast solution to an incompressible flow problem with complex boundaries or multiple moving objects. Various bio-inspired flows of multiple moving objects show that the solver can save over 80% computational time, proportional to the grid reduction when refinement is applied.
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