| 1. |
- Li, Guoqiang, et al.
(författare)
-
A comprehensive dataset of luminescence chronologies and environmental proxy indices of loess-paleosol deposits across Asia
- 2024
-
Ingår i: npj Climate and Atmospheric Science. - : Springer Nature. - 2397-3722. ; 7:1
-
Tidskriftsartikel (refereegranskat)abstract
- Loess-paleosol sequences have been used in Asia to study climate and environmental changes during the Quaternary. The scarcity of age control datasets and proxy indices analysis data for Asian loess has limited our understanding of loess depositional processes and the reconstruction of paleoclimatic changes from loess-paleosol records. In this study, we present a dataset that includes 1785 quartz optically stimulated luminescence ages and 1038 K-feldspar post-infrared infrared stimulated luminescence ages from 128 loess-paleosol sequences located in different regions of Asia. We generate 38 high-resolution age-depth models of loess records based on the provided datasets. We provide data on 12,365 grain size records, 14,964 magnetic susceptibility records, 2204 CaCO3 content records, and 3326 color reflection records. This dataset contains the most detailed and accurate chronologies and proxy index data for loess records in Asia yet published. It provides fundamental data for understanding the spatial-temporal variations in loess depositional processes and climatic changes across the continent during the mid-late Quaternary.
|
|
| 2. |
- Blad, Anton, 1981-
(författare)
-
Low Complexity Techniques for Low Density Parity Check Code Decoders and Parallel Sigma-Delta ADC Structures
- 2011
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, with uncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.In this thesis, a modification to the sum-product decoding algorithm called earlydecision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sumproduct decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization and energy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.
|
|
| 3. |
- Qin, Zidi, et al.
(författare)
-
A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function
- 2020
-
Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 67:12, s. 3422-3426
-
Tidskriftsartikel (refereegranskat)abstract
- In this brief, a novel approximation method and its optimized hardware implementation are proposed for the sigmoid function used in Deep Neural Networks (DNNs). Based on piecewise approximation and truncated Taylor series expansion, the proposed method achieves very good approximation with low complexity while exploiting data representation with powers of two. In addition, by analyzing gradients of the sigmoid function, a small trick is introduced to improve the approximation precision. Furthermore, to reduce the hardware complexity and shorten the critical path, sampled values of the function are generated with simple logical-mapping. It is shown that the proposed approximation schemes can be implemented with purely combinational logic and the sigmoid function can be computed in one clock cycle. The experimental results demonstrate that the mean absolute errors are at the order of 1 x 10(-3). Compared with prior arts, the new design can obtain significant improvement in critical path with comparable performance.
|
|
| 4. |
- Qin, Zidi, et al.
(författare)
-
A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing
- 2020
-
Ingår i: IEEE Access. - : Institute of Electrical and Electronics Engineers (IEEE). - 2169-3536. ; 8, s. 46229-46241
-
Tidskriftsartikel (refereegranskat)abstract
- Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor series expansion is proposed for complex arithmetic functions. Efficient implementations based on unipolar stochastic logic are presented for the monotonic functions. Furthermore, detailed optimization schemes are provided for the non-monotonic functions. Using NAND and AND gates as main computing elements, the optimized hardware architectures have extremely low complexity. The experimental results show that a broad range of arithmetic functions can be implemented with the proposed SC circuits, and the mean absolute errors can achieve the order of 1 x 10(-3). Compared with the state-of-the-art works, the approximation precision for some typical functions can be increased by more than 8x with our method. In addition, the proposed circuits outperform the previous methods in hardware complexity and critical path significantly.
|
|
| 5. |
- Zhou, Jun, et al.
(författare)
-
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices
- 2017
-
Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328. ; 64:9, s. 2495-2507
-
Tidskriftsartikel (refereegranskat)abstract
- Level crossing sampling (LCS) is a power-efficient analog-to-digital conversion scheme for spikelike signals that arise in many Internet of Things-enabled automotive and environmental monitoring applications. However, LCS scheme requires a dedicated time-to-digital converter with large dynamic range specifications. In this paper, we present a compressed LCS that exploits the signal sparsity in the time domain. At the compressed sampling stage, a continuous-time ternary encoding scheme converts the amplitude variations into a ternary timing signal that is captured in a digital random sampler. At the reconstruction stage, a low-complexity split-projection least squares (SPLSs) signal reconstruction algorithm is presented. The SPLS splits random projections and utilizes a standard least squares approach that exploits the ternary-valued amplitude distribution. The SPLS algorithm is hardware friendly, can be run in parallel, and incorporates a low-cost k-term approximation scheme for matrix inversion. The SPLS hardware is analyzed, designed, and implemented in FPGA, achieving the highest data throughput and the power efficiency compared with the prior arts. Simulations of the proposed sampler in an automotive collision warning system demonstrate that the proposed compressed LCS can be very power efficient and robust to wireless interference, while achieving an approximately eightfold data volume compression when compared with Nyquist sampling approaches.
|
|
