| 1. |
- Ahmad, Waqar, et al.
(författare)
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Power Integrity Optimization of 3D Chips Stacked Through TSVs
- 2009
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Ingår i: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS. - NEW YORK : IEEE. - 9781424444489 ; , s. 105-108
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Konferensbidrag (refereegranskat)abstract
- On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.
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| 2. |
- Ebrahimi, Masoumeh, et al.
(författare)
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NoD : Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in 2.5D ICs
- 2017
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Ingår i: 2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS). - : IEEE. - 9781538643792 ; , s. 28-33
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Konferensbidrag (refereegranskat)abstract
- Due to a high cost of 3D IC process technology, the semiconductor industry is targeting 2.5D ICs with interposer as a fast and low-cost alternative to integrate dissimilar technologies. In this paper, we propose an independent network-on-chip die, called Network-on-Die (NoD), for 2.5D ICs that operates as a communication backbone for heterogeneous many-core systems on interposer. NoD is responsible for routing packets from a source router to a destination router, and the connections between routers and cores pass through the interposer. This technique eliminates the complexity of the routing algorithms in heterogeneous systems by turning the irregular form of NoC in 2.5D ICs into a regular/optimized one in NoD. The performance evaluation is verified through RTL simulations for a heterogeneous many-core system of varying die sizes and with asymmetric shapes. We provide the theoretical justification for our simulation results.
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| 3. |
- Grange, Matt, et al.
(författare)
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Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
- 2011
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Ingår i: NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip. - New York, NY, USA : ACM Digital Library. ; , s. 57-64
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Konferensbidrag (refereegranskat)abstract
- A general expression for the average distance for meshes of any dimension and radix, including unequal radices in different dimensions, valid for any traffic pattern under zero-load condition is formulated rigorously to allow its calculation without network-level simulations. The average distance expression is solved analytically for uniform random traffic and for a set of local random traffic patterns. Hot spot traffic patterns are also considered and the formula is empirically validated by cycle true simulations for uniform random, local, and hot spot traffic. Moreover, a methodology to attain closed-form solutions for other traffic patterns is detailed. Furthermore, the model is applied to guide design decisions. Specifically, we show that the model can predict the optimal 3-D topology for uniform and local traffic patterns. It can also predict the optimal placement of hot spots in the network. The fidelity of the approach in suggesting the correct design choices even for loaded and congested networks is surprising. For those cases we studied empirically it is 100%.
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| 4. |
- Grange, Matt, et al.
(författare)
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Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh
- 2009
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Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - San Francisco : IEEE conference proceedings. - 9781424445110 ; , s. 345-351
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Konferensbidrag (refereegranskat)abstract
- The physical performance of a 3-Dimensional Network-on-Chip (NoC) mesh architecture employing through silicon vias (TSV) for vertical connectivity is investigated with a cycle-accurate RTL simulator. The physical latency and area impact of TSVs, switches, and the on-chip interconnect is evaluated to extract the maximum signaling speeds through the switches, horizontal and vertical network links. The relatively low parasitics of TSVs compared to the on-chip 2-D interconnect allow for higher signaling speeds between chip layers. The system-level impact on overall network performance as a result of clocking vertical packets at a higher rate through the TSV interconnect is simulated and reported.
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| 5. |
- Haghbayan, M. -H, et al.
(författare)
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Dark silicon aware power management for manycore systems under dynamic workloads
- 2014
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Ingår i: 2014 32nd IEEE International Conference on Computer Design, ICCD 2014. ; , s. 509-512
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Konferensbidrag (refereegranskat)abstract
- Dark Silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing with each technology generation. We propose a PID (Proportional Integral Derivative) controller based dynamic power management method that considers an upper bound on power consumption (called the Thermal Design Power (TDP)). To avoid violation of the TDP constraint for manycore systems running highly dynamic workloads, it provides fine-grained DVFS (Dynamic Voltage and Frequency Scaling) including near-threshold operation. In addition, the method distinguishes applications with hard Real-Time, soft Real-Time and no Real-Time constraints and treats them with appropriate priorities. In simulations with dynamic workloads mixed-critical application profiles, we show that the method is effective in honoring the TDP bound and it can boost system throughput by over 43% compared to a naive TDP scheduling policy.
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| 6. |
- Rahmani, Amir-Mohammad, et al.
(författare)
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Dynamic Power Management for Many-Core Platforms in the Dark Silicon Era : A Multi-Objective Control Approach
- 2015
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Ingår i: Low Power Electronics and Design (ISLPED), 2015 IEEE/ACM International Symposium on. - : IEEE conference proceedings. - 9781467380089 ; , s. 219-224
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Konferensbidrag (refereegranskat)abstract
- Power management of NoC-based many-core systems with runtime application mapping becomes more challenging in the dark silicon era. It necessitates a multi-objective control approach to consider an upper limit on total power consumption, dynamic behaviour of workloads, processing elements utilization, per-core power consumption, and load on network-on-chip. In this paper, we propose a multi-objective dynamic power management method that simultaneously considers all of these parameters. Fine-grained voltage and frequency scaling, including near-threshold operation, and per-core power gating are utilized to optimize the performance. In addition, a disturbance rejecter is designed that proactively scales down activity in running applications when a new application commences execution, to prevent sharp power budget violations. Simulations of dynamic workloads and mixed time-critical application profiles show that our method is effective in honoring the power budget while considerably boosting the system throughput and reducing power budget violation, compared to the state-of-the-art power management policies.
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| 7. |
- Weldezion, Awet Yemane, et al.
(författare)
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3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture
- 2009
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Ingår i: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION. - NEW YORK : IEEE. - 9781424445110 ; , s. 42-48
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Konferensbidrag (refereegranskat)abstract
- Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid state drives - (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3-D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.
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| 8. |
- Weldezion, Awet Yemane, et al.
(författare)
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A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns
- 2013
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Ingår i: 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013. - : IEEE. - 9781467364843 ; , s. 6702365-
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Konferensbidrag (refereegranskat)abstract
- This paper describes a powerful simulation platform that enables accurate simulations of numerous network configurations under realistic traffic patterns to predict the performance and power needs of a 3-D integrated system early in the design flow. The simulation platform can model virtually any sized 2-D or 3-D network configuration, providing low-cost and fast tradeoff evaluations of various systems architectures. The network simulator uses scalable RTL-level models that can be used for accurate power and timing analyses. We demonstrate the capability of our simulation model by analyzing the performance of various network topologies under spatio-temporal traffic patterns to show how the network topology can be adjusted to meet the performance requirements of a design before it is manufactured. The simulation results can be used to optimize the placement of cores and communication buses early in the flow. By using the model, standard applications such as mobile application processor, femto-cell base-stations on-chip and wide-IO TSV memory stacking can be simulated.
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| 9. |
- Weldezion, Awet Yemane, et al.
(författare)
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Automated Power and Latency Management in Heterogeneous 3D NoCs
- 2015
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Konferensbidrag (refereegranskat)abstract
- Beside different core sizes in many-core Systems-on-Chip, the costand reliability issues of TSVs move 3D NoCs toward heterogonousdesigns. Such heterogeneity introduces design complexity and newchallenges for obtaining a high performance, low power, low area,and a reliable design. By taking all these factors into account, wepropose a design as a combination of Q-Learning and deflectionrouting in a heterogeneous 3D NoCs. This design enables therouting algorithm to dynamically adjust itself to the underlyingtraffic condition and topology arrangement at run time. Thereby,the network can reach its optimal performance and minimum powerconsumption shortly after a reconfiguration either because of anoccurred fault in the network or a traffic change.
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| 10. |
- Weldezion, Awet Yemane, et al.
(författare)
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Bandwidth Optimization for Through Silicon Via(TSV) bundles in 3D Integrated Circuits
- 2009
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Ingår i: DATE'09 Friday Workshops - 3D Integration - Technology, Architecture, Design, Automation, and Test. - Nice, France : DATE Conference. ; , s. 283-287
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Konferensbidrag (refereegranskat)abstract
- Through silicon vias (TSVs) are the backbone of 3D integration technology connecting vertically stacked ICs. Parallel TSVs in the form of bundles are used for vertical signaling.In this paper, we present the ways of maximizing the total bandwidth of a TSV bundle placed in a fixed area by varying the density and the geometries. The ways of optimizing the total bandwidth using analytical methods fora bundle of TSVs placed in a structure with a fixed area and length are examined. The result shows that for uniformly distributed TSVs, maximum bandwidth by proportionalplacement of fewer number of TSV in the bundle can be achieved.
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