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- Melander, Johan, et al.
(författare)
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Implementation of a bit-serial FFT processor with a hierarchical control structure
- 1995
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Ingår i: Proc. 1995 European Conf. on Circuit Theory and Design, ECCTD'95. ; , s. I-423-I-426
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Konferensbidrag (refereegranskat)abstract
- A 128-point FFT/IFFT processor has been designed and implemented in a standard CMOS process using the TSPC logic style. The processor uses a high performance bit-serial SIC architecture and calculates an FFT in 58 ms. A structured technique to derive a hierarchical control structure from the pseudo-code for the FFT has been used, resulting in a control unit implemented as a set of co-operating bit-serial control processors. The computational requirements are met using only one butterfly-PE and two RAMs.
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