| 1. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS
- 2010
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Ingår i: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 29-32
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Konferensbidrag (refereegranskat)abstract
- In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inherent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inherent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit devices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.
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| 2. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
- 2010
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Ingår i: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. - Tampere : www.ieee.org. - 9781424489718 - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
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| 3. |
- Afzal, Nadeem, et al.
(författare)
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A Low-Complexity LMMSE Based Channel Estimation Algorithm for Multiple Standards in Mobile Terminals
- 2010
-
Ingår i: Proceedings of the Swedish System On Chip Conference, SSOCC 2010.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- A less complex and generic channel estimation algorithm for long term evolution (LTE) and digital video broadcasting-handheld (DVB-H) downlink standards, is proposed. The technique, here referred to as minimum mean square error sliding window (MSW) technique, obtains less computational complexity than previous mean squared error (MSE) algorithms [3] at the cost of some 0.3 dB less SNR. The computational complexity is decreased by a factor 3 for the LTE 5-MHz downlink case and by 30 for the DVB-H standard case. Simulated results in terms of mean squared error and bit error rates are presented for a quadrature phase-shift keying (QPSK) systems with interleaving and coding of the data. All simulations are done at the behaviolar-level level.
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| 4. |
- Afzal, Nadeem, et al.
(författare)
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A study on power consumption of modified noise-shaper architectures for Sigma-Delta DACs
- 2011
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Ingår i: Circuit Theory and Design (ECCTD), 2011. - : IEEE. - 9781457706172 ; , s. 274-277
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Konferensbidrag (refereegranskat)abstract
- In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work as a composite architecture (CA), shows about 9 dB increase in SNR while maintaining a power-consumption at the same level as that of a so-called hybrid architecture (HA). The power estimation is done for modulators on the RTL level using a standard cell library in a 65-nm technology. The modulators are operated at a sampling frequency of 2 GHz.
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| 5. |
- Afzal, Nadeem
(författare)
-
Complexity and Power Reduction in Digital Delta-Sigma Modulators
- 2014
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.
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| 6. |
- Afzal, Nadeem, et al.
(författare)
-
Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
- 2012
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.
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| 7. |
- Afzal, Nadeem, et al.
(författare)
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On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators
- 2012
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- In order to determine a maximum allowed input scale for the stable operation of higher-order delta-sigma modulators, the designers largely depend on the analytical and numerical analysis. In this brief, the maximum allowed input scale to a multi-bit digital error-feedback deltasigma modulator of arbitrary order is derived, mathematically. The digital modulator with an arbitrary output word length is stable if its output does not overflow. Thus, to avoid overflow of the modulator output, the relations between the peak values of the involved digital signals are devised. A number of example configurations are presented to illustrate the usefulness of the derivations.
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| 8. |
- Afzal, Nadeem, et al.
(författare)
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Power efficient arrangement of oversampling sigma-delta DAC
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 - 9781467322225 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.
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| 9. |
- Afzal, Nadeem, et al.
(författare)
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Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
- 2014
-
Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:9, s. 641-645
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.
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| 10. |
- Afzal, Nadeem, et al.
(författare)
-
Study of modified noise-shaper architectures for oversampled sigma-delta DACs
- 2010
-
Ingår i: NORCHIP, 2010. - : IEEE. - 9781424489725 ; , s. 1-4
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- In this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.
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