| 1. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 1.2-V pseudo-differential OTA with common-mode feedforward in 65-nm CMOS
- 2010
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Ingår i: Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 29-32
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Konferensbidrag (refereegranskat)abstract
- In this work, we describe the implementation of a 1. 2-V pseudo-differential operational transconductance amplifier (OTA) with common-mode feedforward (CMFF) and inherent common-mode feedback (CMFB) in a 65-nm, digital CMOS process. The OTA architecture provides an inherent CMFB when cascaded OTA structures are utilized andthis work has studied a cascaded amplifier consisting of fourstages. Due to the low-gain using core 65-nm circuit devices, the overall gain must be distributed on all four stages to acquire a gain of more than 60 dB, while maintaining a-3-dB bandwidth of 200 MHz. To achieve high gain, we propose using a modified, positive-feedback, cross-coupled input differential stage. The modified OTA achieves a high output swing of ± 0.85 V due to only two stacked transistors, 88 dB DC gain and a third-order harmonic of -60 dB for 800 mVpp at 30 MHz. Further on, in a capacitive buffer configuration, we achieve a high slew rate of 1240 V/µS, -3-dB bandwidth of 509 MHz, signal-to-noise ratio of 63 dB while consuming 10.4 mW power.
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| 2. |
- Aamir, Syed Ahmed, 1980-, et al.
(författare)
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A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
- 2010
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Ingår i: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10. - Tampere : www.ieee.org. - 9781424489718 - 9781424489725 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
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| 3. |
- Afzal, Nadeem, et al.
(författare)
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Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
- 2012
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.
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| 4. |
- Afzal, Nadeem, et al.
(författare)
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On Scaling and Output Cardinality of Multi-Bit Digital Error-Feedback Modulators
- 2012
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Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
- In order to determine a maximum allowed input scale for the stable operation of higher-order delta-sigma modulators, the designers largely depend on the analytical and numerical analysis. In this brief, the maximum allowed input scale to a multi-bit digital error-feedback deltasigma modulator of arbitrary order is derived, mathematically. The digital modulator with an arbitrary output word length is stable if its output does not overflow. Thus, to avoid overflow of the modulator output, the relations between the peak values of the involved digital signals are devised. A number of example configurations are presented to illustrate the usefulness of the derivations.
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| 5. |
- Afzal, Nadeem, et al.
(författare)
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Power efficient arrangement of oversampling sigma-delta DAC
- 2012
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Ingår i: NORCHIP, 2012. - : IEEE. - 9781467322218 - 9781467322225 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.
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| 6. |
- Ahmed Aamir, Syed, et al.
(författare)
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Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers
- 2013
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS), 2013. - : IEEE conference proceedings. - 9781467357609 ; , s. 381-384
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Konferensbidrag (refereegranskat)abstract
- This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.
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| 7. |
- Alvbrant, Joakim, 1973-
(författare)
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A study on emerging electronics for systems accepting soft errors
- 2016
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Moore’s law has until today mostly relied on shrinkage of the size of the devices inintegrated circuits. However, soon the granularity of the atoms will set a limit together with increased error probability of the devices. How can Moore’s law continue in thefuture? To overcome the increased error rate, we need to introduce redundancy. Applyingmethods from biology may be a way forward, using some of the strategies that transformsan egg into a fetus, but with electronic cells.A redundant system is less sensitive to failing components. We define electronic clayas a massive redundancy system of interchangeable and unified subsystems. We show how a mean voter, which is simpler than a majority voter, impact a redundant systemand how optimization can be formalized to minimize the impact of failing subsystems.The performance at given yield can be estimated with a first order model, without the need for Monte-Carlo simulations. The methods are applied and verified on a redundant finite-impulse response filter.The elementary circuit behavior of the memristor, ”the missing circuit element”, is investigated for fundamental understanding and how it can be used in applications. Different available simulation models are presented and the linear drift model is simulated with Joglekar-Wolf and Biolek window functions. Driven by a sinusoidal current, the memristor is a frequency dependent component with a cut-off frequency. The memristor can be densely packed and used in structures that both stores and compute in the same circuit, as neurons do. Surrounding circuit has to affect (write) and react (read) to the memristor with the same two terminals.We looked at artificial neural network for pattern recognition, but also for self organization in electronic cell array. Finally we look at wireless sensor network and how such system can adopt to the environment. This is also a massive redundant clay-like system.Future electronic systems will be massively redundant and adaptive. Moore’s law will continue, not based on shrinking device sizes, but on cheaper, numerous, unified and interchangeable subsystems.
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| 8. |
- Alvbrant, Joakim, 1973-, et al.
(författare)
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Study and Simulation Example of a Redundant FIR Filter
- 2012
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Ingår i: Proceedings 30th Norchip Conference. - : IEEE. - 9781467322225 - 9781467322218 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture.
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| 9. |
- Harikumar, Prakash, et al.
(författare)
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A Study on Switched-Capacitor Blocks for Reconfigurable ADCs
- 2011
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Ingår i: Electronics, Circuits and Systems (ICECS), 2011. - 9781457718458 ; , s. 649-652
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Konferensbidrag (refereegranskat)abstract
- Pipelined analog-to-digital converters (ADCs) achieve low to moderate resolutions at high bandwidths while sigma-delta (ΣΔ) ADCs provide high resolution at moderate bandwidths. A switched-capacitor (SC) block which can function as an integrator or an MDAC can be used to implement a reconfigurable ADC (R-ADC) which supports both these types of architectures. Through the use of high level models this work attempts to derive the capacitance and critical opamp parameters such as DC gain and bandwidth of the SC blocks in a reconfigurable ADC. Scaling of capacitance afforded by the noise shaping property of ΣΔ loops as well as the inter-stage gain of pipelined ADCs is used to minimize the total capacitance. This work can be used as reference material to understand some of the design trade-offs in R-ADCs.sigma-delta ADCs
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| 10. |
- Kazim, Muhammad Irfan, et al.
(författare)
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An Efficient Full-Wave Electromagnetic Analysis for Capacitive Body-Coupled Communication
- 2015
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Ingår i: International Journal of Antennas and Propagation. - : Hindawi Limited. - 1687-5869 .- 1687-5877. ; 2015, s. 15-
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Tidskriftsartikel (refereegranskat)abstract
- Measured propagation loss for capacitive body-coupled communication (BCC) channel (1 MHz to 60 MHz) is limitedly available in the literature for distances longer than 50 cm. This is either because of experimental complexity to isolate the earth-ground or design complexity in realizing a reliable communication link to assess the performance limitations of capacitive BCC channel. Therefore, an alternate efficient full-wave electromagnetic (EM) simulation approach is presented to realistically analyze capacitive BCC, that is, the interaction of capacitive coupler, the human body, and the environment all together. The presented simulation approach is first evaluated for numerical/human body variation uncertainties and then validated with measurement results from literature, followed by the analysis of capacitive BCC channel for twenty different scenarios. The simulation results show that the vertical coupler configuration is less susceptible to physiological variations of underlying tissues compared to the horizontal coupler configuration. The propagation loss is less for arm positions when they are not touching the torso region irrespective of the communication distance. The propagation loss has also been explained for complex scenarios formed by the ground-plane and the material structures (metals or dielectrics) with the human body. The estimated propagation loss has been used to investigate the link-budget requirement for designing capacitive BCC system in CMOS sub-micron technologies.
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