| 1. |
- Li, Junjie, et al.
(författare)
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A Novel Dry Selective Isotropic Atomic Layer Etching of SiGe for Manufacturing Vertical Nanowire Array with Diameter Less than 20 nm
- 2020
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Ingår i: Materials. - : MDPI AG. - 1996-1944. ; 13:3
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Tidskriftsartikel (refereegranskat)abstract
- Semiconductor nanowires have great application prospects in field effect transistors and sensors. In this study, the process and challenges of manufacturing vertical SiGe/Si nanowire array by using the conventional lithography and novel dry atomic layer etching technology. The final results demonstrate that vertical nanowires with a diameter less than 20 nm can be obtained. The diameter of nanowires is adjustable with an accuracy error less than 0.3 nm. This technology provides a new way for advanced 3D transistors and sensors.
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| 2. |
- Lixing, Zhou, et al.
(författare)
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Understanding dipole formation at dielectric/dielectric hetero-interface
- 2018
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 113:18
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Tidskriftsartikel (refereegranskat)abstract
- Band alignment and dipole formation at the hetero-interface still remain fascinating and, hence, are being intensively investigated. In this study, we experimentally investigate the dipole formation by employing a dielectric/dielectric (Al2O3/GeO2) interface. We investigate the dipole dependence on various post-deposition annealing (PDA) ambiences from the viewpoints of electrical extraction and the X-ray photoelectron spectroscopy measurement. The core level shift at the Al2O3/GeO2 interface is consistent with the dipole changes in various PDA ambiences. We discover that the dipole formation can be well explained by the interface gap state and charge neutrality level theory. These results further confirm the feasibility of gap state theory in explaining the band alignment at hetero-junctions. This study can be a booster to enhance the comprehension of dipole origin at hetero-junction interfaces.
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| 3. |
- Qin, Changliang, et al.
(författare)
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Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs
- 2016
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Ingår i: Solid-State Electronics. - : Elsevier. - 0038-1101 .- 1879-2405. ; 123, s. 38-43
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device's performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID-VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on-off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.
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| 4. |
- Radamson, Henry H., et al.
(författare)
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Miniaturization of CMOS
- 2019
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Ingår i: Micromachines. - : MDPI AG. - 2072-666X. ; 10:5
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Tidskriftsartikel (refereegranskat)abstract
- When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.
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| 5. |
- Radamson, Henry H., et al.
(författare)
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State of the Art and Future Perspectives in Advanced CMOS Technology
- 2020
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Ingår i: Nanomaterials. - : MDPI AG. - 2079-4991. ; 10:8
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Forskningsöversikt (refereegranskat)abstract
- The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.
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| 6. |
- Radamson, Henry H., et al.
(författare)
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The Challenges of Advanced CMOS Process from 2D to 3D
- 2017
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Ingår i: Applied Sciences. - : MDPI AG. - 2076-3417. ; 7:10
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Forskningsöversikt (refereegranskat)abstract
- The architecture, size and density of metal oxide field effect transistors (MOSFETs) as unit bricks in integrated circuits (ICs) have constantly changed during the past five decades. The driving force for such scientific and technological development is to reduce the production price, power consumption and faster carrier transport in the transistor channel. Therefore, many challenges and difficulties have been merged in the processing of transistors which have to be dealed and solved. This article highlights the transition from 2D planar MOSFETs to 3D fin field effective transistors (FinFETs) and then presents how the process flow faces different technological challenges. The discussions contain nano-scaled patterning and process issues related to gate and (source/drain) S/D formation as well as integration of III-V materials for high carrier mobility in channel for future FinFETs.
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| 7. |
- Wang, Xiaolei, et al.
(författare)
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Physically Based Evaluation of Effect of Buried Oxide on Surface Roughness Scattering Limited Hole Mobility in Ultrathin GeOI MOSFETs
- 2017
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0018-9383 .- 1557-9646. ; 64:6, s. 2611-2616
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a numerical simulation study investigating the effect of buried oxide on surface roughness scattering limited hole mobility (mu(SR)) in ultrathin germanium-on-insulator (GeOI) MOSFETs, for the first time. The simulation considers wave function penetration at channel/oxide interface and nonlinear dependence of scattering matrix element on surface fluctuation. Three types of buried oxide materials are compared (GeO2, SiO2, and Si3N4). The mu(SR) increases in the order of SiO2 < GeO2 < Si3N4. This dependence of mu(SR) on buried oxide material is due to surface fluctuation scattering from backside Ge/buried oxide interface. Our simulation results show that Si3N4 and GeO2 are beneficial as buried oxide for mobility enhancement in GeOI MOSFETs, compared with conventional SiO2 as buried oxide. Our findings provide an insight into further improving mobility characteristic.
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