| 1. |
- Ahlberg, Patrik, et al.
(författare)
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Graphene as a Diffusion Barrier in Galinstan-Solid Metal Contacts
- 2014
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 61:8, s. 2996-3000
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the use of graphene as a diffusion barrier to a eutectic Ga-In-Sn alloy, i.e., galinstan, for electrical contacts in electronics. Galinstan is known to be incompatible with many conventional metals used for electrical contacts. When galinstan is in direct contact with Al thin films, Al is readily dissolved leading to the formation of Al oxides present on the surface of the galinstan droplets. This reaction is monitored ex situ using several material analysis methods as well as in situ using a simple circuit to follow the time-dependent resistance variation. In the presence of a multilayer graphene diffusion barrier, the Al-galinstan reaction is effectively prevented for galinstan deposited by means of drop casting. When deposited by spray coating, the high-impact momentum of the galinstan droplets causes damage to the multilayer graphene and the Al-galinstan reaction is observed at some defective spots. Nonetheless, the graphene barrier is likely to block the formation of Al oxides at the Al/galinstan interface leading to a stable electrical current in the test circuit.
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| 2. |
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| 3. |
- Asad, Muhammad, 1986, et al.
(författare)
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Enhanced high-frequency performance of top-gated graphene FETs due to substrate-induced improvements in charge carrier saturation velocity
- 2021
-
Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 68:2, s. 899-902
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Tidskriftsartikel (refereegranskat)abstract
- High-frequency performance of top-gated graphene field-effect transistors (GFETs) depends to a large extent on the saturation velocity of the charge car-riers, a velocity limited by inelastic scattering by surface optical phonons from the dielectrics surrounding the chan-nel. In this work, we show that by simply changing the graphene channel surrounding dielectric with a material having higher optical phonon energy, one could improve the transit frequency and maximum frequency of oscillation of GFETs. We fabricated GFETs on conventional SiO2/Si substrates by adding a thin Al2O3 interfacial buffer layer on top of SiO2/Si substrates, a material with about 30% higher optical phonon energy than that of SiO2, and compared performance with that of GFETs fabricated without adding the interfacial layer. From S-parameter measurements, a transit frequency and a maximum frequency of oscillation of 43 GHz and 46 GHz, respectively, were obtained for GFETs on Al2O3 with 0.5 µm gate length. These values are approximately 30% higher than those for state-of-the-art GFETs of the same gate length on SiO2. For relating the improvement of GFET high-frequency performance to improvements in the charge carrier saturation velocity, we used standard methods to extract the charge carrier veloc-ity from the channel transit time. A comparison between two sets of GFETs with and without the interfacial Al2O3 layer showed that the charge carrier saturation velocity had increased to 2·10^7 cm/s from 1.5·10^7 cm/s.
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| 4. |
- Axelsson, Olle, 1986, et al.
(författare)
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Application Relevant Evaluation of Trapping Effects in AlGaN/GaN HEMTs With Fe-Doped Buffer
- 2016
-
Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 63:1, s. 326-332
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Tidskriftsartikel (refereegranskat)abstract
- This paper investigates the impact of different iron (Fe) buffer doping profiles on trapping effects in microwave AlGaN/gallium nitride (GaN) high electron mobility transistors (HEMTs). We characterize not only the current collapse due to trapping in the buffer, but also the recovery process, which is important in the analysis of suitable linearization schemes for amplitude modulated signals. It is shown that the simple pulsed dc measurements of current transients can be used to investigate transient effects in the RF power. Specifically, it is revealed that the design of the Fe-doping profile in the buffer greatly influences the recovery time, with the samples with lower Fe concentration showing slower recovery. In contrast, traditional indicators, such as S-parameters and dc as well as pulsed $I$-$V$ characteristics, show very small differences. An analysis of the recovery shows that this effect is due to the presence of two different detrapping processes with the same activation energy (0.6 eV) but different time constants. For highly doped buffers, the faster process dominates, whereas the slower process is enhanced for less doped buffers.
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| 5. |
- Bakowski, Mietek, et al.
(författare)
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Design and characterization of newly developed 10 kV 2 A SiC p-i-n diode for soft-switching industrial power supply
- 2015
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Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers Inc.. - 0018-9383 .- 1557-9646. ; 62:2, s. 366-373
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Tidskriftsartikel (refereegranskat)abstract
- 10 kV, 2 A SiC p-i-n diodes have been designed and fabricated. The devices feature excellent stability of forward characteristics and robust junction termination with avalanche capability of 1 J. The fabricated diodes have been electrically evaluated with respect to dynamic ON-state voltage, reverse recovery behavior, bipolar stability, and avalanche capability. More than 60% reduction of losses has been demonstrated using newly developed 10-kV p-i-n diodes in a multikilowatt high voltage, high-frequency dc/dc soft-switching converter
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| 6. |
- Bengtsson, Olof, et al.
(författare)
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Investigation of SOI-LDMOS for RF-power applications using Computational Load-Pull
- 2009
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE. - 0018-9383 .- 1557-9646. ; 56:3, s. 505-511
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Tidskriftsartikel (refereegranskat)abstract
- Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the OFF-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high OFF-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed ON-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.
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| 7. |
- Bergsten, Johan, 1988, et al.
(författare)
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Electron Trapping in Extended Defects in Microwave AlGaN/GaN HEMTs with Carbon-Doped Buffers
- 2018
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1557-9646 .- 0018-9383. ; 65:6, s. 2446-2453
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Tidskriftsartikel (refereegranskat)abstract
- This paper investigates AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on epistructures with carbon (C)-doped buffers. Metalorganic chemical vapor deposition is used to grow two C-doped structures with different doping profiles, using growth parameters to change the C incorporation. The C concentration is low enough to result in n-type GaN. Reference devices are also fabricated on a structure using iron (Fe) as dopant, to exclude any process related variations and provide a relevant benchmark. All devices exhibit similar dc performance. However, pulsed I - V$ measurements show extensive dispersion in the C-doped devices, with values of dynamic R-mathrm-scriptscriptstyle ON 3 -4 times larger than in the dc case. Due to the extensive trapping, the devices with C-doped buffers can only supply about half the output power of the Fe-doped sample, 2.5 W/mm compared to 4.8 W/mm at 10 GHz. In drain current transient measurements, the trap filling time is varied, finding large prevalence of trapping at dislocations for the C-doped samples. Clusters of C around the dislocations are suggested to be the main cause for the increased dispersion.
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| 8. |
- Bergsten, Johan, et al.
(författare)
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Performance Enhancement of Microwave GaN HEMTs Without an AlN-Exclusion Layer Using an Optimized AlGaN/GaN Interface Growth Process
- 2016
-
Ingår i: IEEE Transactions on Electron Devices. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0018-9383 .- 1557-9646. ; 63:1, s. 333-338
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Tidskriftsartikel (refereegranskat)abstract
- The impact of the sharpness of the AlGaN/GaN interface in high-electron mobility transistors (HEMTs) is investigated. Two structures, one with an optimized AlGaN/GaN interface and another with an unoptimized, were grown using hot-wall metal-organic chemical vapor deposition. The structure with optimized sharpness of the interface shows electron mobility of 1760 cm(2)/V . s as compared with 1660 cm(2)/V . s for the nonoptimized interface. Gated Hall measurements indicate that the sharper interface maintains higher mobility when the electrons are close to the interface compared with the nonoptimized structure, indicating less scattering due to alloy disorder and interface roughness. HEMTs were processed and evaluated. The higher mobility manifests as lower parasitic resistance yielding a better dc and high-frequency performance. A small-signal equivalent model is extracted. The results indicate a lower electron penetration into the buffer in the optimized sample. Pulsed-IV measurements imply that the sharper interface provides less dispersive effects at large drain biases. We speculate that the mobility enhancement seen AlGaN/AlN/GaN structures compared with the AlGaN/GaN case is not only related to the larger conduction band offset but also due to a more welldefined interface minimizing scattering due to alloy disorder and interface roughness.
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| 9. |
- Bergsten, Johan, 1988, et al.
(författare)
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Performance Enhancement of Microwave GaN HEMTs Without an AlN-Exclusion Layer Using an Optimized AlGaN/GaN Interface Growth Process
- 2016
-
Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 1557-9646 .- 0018-9383. ; 63:1, s. 333-338
-
Tidskriftsartikel (refereegranskat)abstract
- The impact of the sharpness of the AlGaN/GaN interface in high-electron mobility transistors (HEMTs) is investigated. Two structures, one with an optimized AlGaN/GaN interface and another with an unoptimized, were grown using hot-wall metal-organic chemical vapor deposition. The structure with optimized sharpness of the interface shows electron mobility of 1760 cm(2)/V . s as compared with 1660 cm(2)/V . s for the nonoptimized interface. Gated Hall measurements indicate that the sharper interface maintains higher mobility when the electrons are close to the interface compared with the nonoptimized structure, indicating less scattering due to alloy disorder and interface roughness. HEMTs were processed and evaluated. The higher mobility manifests as lower parasitic resistance yielding a better dc and high-frequency performance. A small-signal equivalent model is extracted. The results indicate a lower electron penetration into the buffer in the optimized sample. Pulsed-IV measurements imply that the sharper interface provides less dispersive effects at large drain biases. We speculate that the mobility enhancement seen AlGaN/AlN/GaN structures compared with the AlGaN/GaN case is not only related to the larger conduction band offset but also due to a more welldefined interface minimizing scattering due to alloy disorder and interface roughness.
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| 10. |
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| 11. |
- Bonmann, Marlene, 1988, et al.
(författare)
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Effects of self-heating on fT and fmax performance of graphene field-effect transistors
- 2020
-
Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 67:3, s. 1277-1284
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Tidskriftsartikel (refereegranskat)abstract
- It has been shown that there can be a significant temperature increase in graphene field-effect transistors (GFETs) operating under high drain bias, which is required for power gain. However, the possible effects of self-heating on the high-frequency performance of GFETs have been weakly addressed so far. In this article, we report on an experimental and theoretical study of the effects of self-heating on dc and high-frequency performance of GFETs by introducing a method that allows accurate evaluation of the effective channel temperature of GFETs with a submicrometer gate length. In the method, theoretical expressions for the transit frequency (fT) and the maximum frequency of oscillation (fmax) based on the small-signal equivalent circuit parameters are used in combination with the models of the field- and temperature-dependent charge carrier concentration, velocity, and saturation velocity of GFETs. The thermal resistances found by our method are in good agreement with those obtained by the solution of the Laplace equation and by the method of thermo-sensitive electrical parameters. Our experiments and modeling indicate that the self-heating can significantly degrade the fT and fmax of GFETs at power densities above 1 mW/μm², from approximately 25 to 20 GHz. This article provides valuable insights for further development of GFETs, taking into account the self-heating effects on the high-frequency performance.
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| 12. |
- Borg, Johan, et al.
(författare)
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Evaluation of a surface-channel CCD manufactured in a pinned active-pixel-sensor CMOS process
- 2011
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 58:8, s. 2660-2664
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents measurements on a surfacechannel CCD with gates implemented using single-layer polysilicongates. The device was manufactured in a 0.18 μm PINNEDphoto diode CMOS process commercially available from UMC.The CCD was built with a field-plate covering all gates as wellas the space between them, which allows the potential in the gapbetween non-overlapping gates to be manipulated.We present charge transfer efficiency measurements performedat clock frequencies of 1 MHz and 5 MHz, at multiplebackground packet sizes, and field-plate voltages. We furtherpropose and apply a method for separating CTI in four-phaseCCDs due to trapping from the inefficiency stemming from otherphenomena.The measurements show a single stage CTI ranging from 1.7×10−4 with a moderate background charge and substantial fieldplatevoltage, to 0.007 at zero field-plate voltage and the highestbackground charge tested. The CTI can be reduced significantly(more than a factor of 10 in some cases) by applying a significantnegative voltage at the field-plate. This, and the fact that only aminor part of the CTI can be attributed to trapping, indicatesthat the performance of the device is limited by the presence ofpotential hollows in the gaps between the gates.
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| 13. |
- Bremer, Johan, 1991, et al.
(författare)
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Electric-Based Thermal Characterization of GaN Technologies Affected by Trapping Effects
- 2020
-
Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 67:5, s. 1952-1958
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Tidskriftsartikel (refereegranskat)abstract
- This article presents an electric-based methodology for thermal characterization of semiconductor technologies. It is shown that for technologies such as gallium nitride (GaN) high electron mobility transistors, which exhibit several field induced electron trapping effects, the thermal characterization has to be performed under specific conditions. The electric field is limited to low levels to avoid activation of trap states. At the same time, the dissipated power needs to be high enough to change the operating temperature of the device. The method is demonstrated on a test structure implemented as a GaN resistor with large contact separation. It is used to evaluate the thermal properties of samples with different silicon carbide suppliers and buffer thickness.
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| 14. |
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| 15. |
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| 16. |
- Buono, Benedetto, et al.
(författare)
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Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs
- 2010
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 57:10, s. 2664-2670
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Tidskriftsartikel (refereegranskat)abstract
- The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.
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| 17. |
- Buono, Benedetto, et al.
(författare)
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Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs
- 2010
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Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9383 .- 1557-9646. ; 57:3, s. 704-711
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Tidskriftsartikel (refereegranskat)abstract
- Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.
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| 18. |
- Buono, Benedetto, et al.
(författare)
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Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs
- 2011
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 58:7, s. 2081-2087
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Tidskriftsartikel (refereegranskat)abstract
- The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.
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| 19. |
- Cha, Eunjung, 1985, et al.
(författare)
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Optimization of Channel Structures in InP HEMT Technology for Cryogenic Low-Noise and Low-Power Operation
- 2023
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Ingår i: IEEE Transactions on Electron Devices. - 1557-9646 .- 0018-9383. ; 70:5, s. 2431-2436
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Tidskriftsartikel (refereegranskat)abstract
- We report the impact from channel composition on the cryogenic low-noise performance at low dc power for a 100-nm gate-length InGaAs-InAlAs-InP high-electron mobility transistor (HEMT). Two indium (In) channel compositions, 65% and 80%, were studied by dc and RF characterization at 300 and 5 K. For the cryogenic low-noise optimization, it was important to increase the transconductance to gate–source capacitance ratio in the weak inversion region implying that a higher maximum cutoff frequency in the HEMT does not guarantee lower noise. The HEMT noise performance was obtained from noise measurements in a hybrid three-stage 4–8-GHz ( $\textit{C}$ -band) low-noise amplifier (LNA) down to 300- $\mu$ W dc power dissipation. While the HEMT LNA noise performance for both the channel compositions at 300 K was found to be comparable, the HEMT LNA at 5 K with 65% In channel showed a minimum noise temperature of 1.4 K, whereas the noise temperature in the HEMT LNA with 80% In channel HEMTs increased to 2.4 K. The difference in the noise became more pronounced at reduced dc power dissipation. The ultralow dc power of 300 $\mu$ W demonstrated for a cryogenic $\textit{C}$ -band LNA with an average noise temperature of 2.9 K and 24-dB gain is of interest for future qubit read-out electronics at 4 K.
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| 20. |
- Chen, Tingsu, et al.
(författare)
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Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I : Analytical Model of the MTJ STO
- 2015
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 62:3, s. 1037-1044
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Tidskriftsartikel (refereegranskat)abstract
- Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.
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| 21. |
- Chen, Tingsu, et al.
(författare)
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Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II : Verilog-A Model Implementation
- 2015
-
Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 62:3, s. 1045-1051
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Tidskriftsartikel (refereegranskat)abstract
- The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.
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| 22. |
- Chen, Xi, et al.
(författare)
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Low-Noise Schottky Junction Trigate Silicon Nanowire Field-effect Transistor for Charge Sensing
- 2019
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 66:9, s. 3994-4000
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Tidskriftsartikel (refereegranskat)abstract
- Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage.
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| 23. |
- Corman, Thierry, et al.
(författare)
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Burst technology with feedback-loop control for capacitive detection and electrostatic excitation of resonant silicon sensors
- 2000
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Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9383 .- 1557-9646. ; 47:11, s. 2228-2235
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Tidskriftsartikel (refereegranskat)abstract
- A method for excitation and detection of resonant silicon sensors based on discontinuous, burst excitation is presented. The solution eliminates the crosstalk between electrostatic excitation and capacitive detection by separating them in time. High excitation voltages can be combined with highly sensitive detection electronics. The method facilitates the use of large distances between the resonator and electrodes used for elicitation and detection. The method was successfully tested with feedback-loop control on silicon resonant density and pressure sensors where the electrodes were positioned outside a glass, Continuous measurements of gas pressures and liquid densities were realized, The simplified fabrication process utilized reduces the risk of leakage from the ambient pressure to the low-pressure cavities in which the resonators are encapsulated since electrical feedthroughs are not needed, Excitation voltages alternating between 0 and 150 V could be applied to the resonators with measured electronics sensitivities of 0.4 fF Signal-to-noise ratios (SNRs) as high as 100 (density sensor) and 360 (pressure sensor) were obtained. The electronic evaluation revealed that the burst duty cycle (i.e,, the excitation time relative to the free oscillation time) had a strong influence on the output detection voltage, As few as two excitation periods with a burst cycle frequency of 115 Hz and a burst duty cycle of 1% was sufficient to select and lock the resonance frequency (28 042 Hz) for the tested pressure sensor. The same electrodes could be used for both excitation and detection, A novel solution is also presented that eliminates the charging effect of dielectric surfaces which otherwise can be a problem for capacitive detection.
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| 24. |
- Danielsson, E., et al.
(författare)
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Fabrication and characterization of heterojunction diodes with HVPE-Grown GaN on 4H-SiC
- 2001
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Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9383 .- 1557-9646. ; 48:3, s. 444-449
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Tidskriftsartikel (refereegranskat)abstract
- GaN/SiC heterojunctions can improve the performance considerably for BJTs and FETs. In this work, heterojunction diodes have been manufactured and characterized. The fabricated diodes have a GaN n-type cathode region on top of a JH-SIC p-type epi layer. The GaN layer was grown with HVPE directly on off-axis SiC without a buffer layer. Mesa structures were formed and a Ti metallization was used as cathode contact to GaN, and the anode contact was deposited on the backside using sputtered Al. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed on the diode structures. The ideality factor of the measured diodes was 1.1 and was constant with temperature. A built in potential of 2.06 V was extracted from I-V-measurements and agrees well with the built in potential from C-V-measurements. The conduction band offset was extracted to 1.1 eV and the heterojunction was of type II. The turn on voltage for the diodes is about 1 V lower than expected and a suggested mechanism for this effect is discussed.
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| 25. |
- Del Castillo, Ragnar Ferrand-Drake, et al.
(författare)
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Characterization of Trapping Effects Related to Carbon Doping Level in AlGaN Back-Barriers for AlGaN/GaN HEMTs
- 2024
-
Ingår i: IEEE Transactions on Electron Devices. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0018-9383 .- 1557-9646.
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Tidskriftsartikel (refereegranskat)abstract
- The impact of different carbon concentrations in the Al 0.06 Ga 0.94 N graded back-barrier and GaN buffer of high electron mobility transistors (HEMTs) is investigated. Four epi-wafers with different carbon concentrations, ranging from 1 x 10(17) to 5 x 10(17) cm( -3) , were grown by metal organic chemical vapor deposition (MOCVD). HEMTs with 100 and 200 nm gate lengths were fabricated and characterized with dc, Pulsed-IV, drain current transient spectroscopy (DCTS), and large-signal measurements at 30 GHz. It is shown that the back-barrier effectively prevents buffer-related electron trapping. The highest C-doping provides the best 2DEG confinement, while lower carbon doping levels are beneficial for a high output power and efficiency. A C-doping of 1 x 10(17)cm( -3) offers the highest output power at maximum power added efficiency (PAE) (1.8 W/mm), whereas 3 x 10(17) cm( -3) doping provides the highest PAE ( > 40%). The C-profiles acquired by using secondary ion mass spectroscopy (SIMS), in combination with DCTS, is used to explain the electron trapping effects. Traps associated with the C-doping in the back-barrier are identified and the bias ranges for the trap activation are discussed. The study shows the importance of considering the C-doping level in the back-barrier of microwave GaN HEMTs for power amplification and generation.
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