| 1. |
- Herrholz, Andreas, et al.
(författare)
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The ANDRES Project : Analysis and Design of run-time Reconfigurable, heterogeneous Systems
- 2007
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Ingår i: Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL. - : IEEE. - 9781424410606 - 1424410606 ; , s. 396-401
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Konferensbidrag (refereegranskat)abstract
- Today's heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of these systems is still a complex and error-prone task due to the different Models of Computations (MoCs), design languages and tools associated with each of the domains. Though making such systems adaptive is technologically feasible, most of the current design methodologies do not explicitely support adaptive architectures. This paper present the ANDRES project. The main objective of ANDRES is the development of a seamless design flow for adaptive heterogeneous embedded systems (AHES) based on the modelling language SystemC. Using domain-specific modelling extensions and libraries, ANDRES will provide means to efficiently use and exploit adaptivity in embedded system design. The design flow is completed by a methodology and tools for automatic hardware and software synthesis for adaptive architectures.
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| 2. |
- Ehliar, Andreas, et al.
(författare)
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An FPGA based Open Source Network-on-chip Architecture
- 2007
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Ingår i: 17th International Conference on Fileld Programmable Logic and Applications, FPL, Amsterdam, Holland, 2007. - : IEEE. - 9781424410606 ; , s. 800-803
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Konferensbidrag (refereegranskat)abstract
- Networks on chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.
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