| 1. |
- Ahmad, Waqar
(författare)
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Core Switching Noise for On-Chip 3D Power Distribution Networks
- 2012
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Reducing the interconnect size with each technology node and increasing speed with each generation increases IR-drop and Ldi/dt noise. In addition to this, the drive for more integration increases the average current requirement for modern ULSI design. Simultaneous switching of core logic blocks and I/O drivers produces large current transients due to power distribution network parasitics at high clock frequency. The current transients are injected into the power distribution planes thereby inducing noise in the supply voltage. The part of the noise that is caused by switching of the internal logic load is core switching noise. The core logic switches at much higher speed than driver speed whereas the package inductance is less than the on-chip inductance in modern BGA packages. The core switching noise is currently gaining more attention for three-dimensional integrated circuits where on-chip inductance is much higher than the board and package inductance due to smaller board, and package. The switching noise of the driver is smaller than the core switching noise due to small driver size and reduced capacitance associated with short on-board wires for three-dimensional integrated circuits. The load increases with the addition of each die. The power distribution TSV pairs to supply each extra die also introduce additional parasitic. The core switching noise may propagate through substrate and consequently through interconnecting TSVs to different dies in heterogeneous integrated system. Core switching noise may lead to decreased device drive capability, increased gate delays, logic errors, and reduced noise margins. The actual behavior of the on-chip load is not well known in the beginning of the design cycle whereas altering the design during later stages is not cost effective. The size of a three-dimensional power distribution network may reach billions of nodes with the addition of dies in a vertical stack. The traditional tools may run out of time and memory during simulation of a three-dimensional power distribution network whereas, the CAD tools for the analysis of 3D power distribution network are in the process of evolution. Compact mathematical models for the estimation of core switching noise are necessary in order to overcome the power integrity challenges associated with the 3D power distribution network design. This thesis presents three different mathematical models to estimate core switching noise for 3D stacked power distribution networks. A time-domain-based mathematical model for the estimation of design parameters of a power distribution TSV pair is also proposed. Design guidelines for the estimation of optimum decoupling capacitance based on flat output impedance are also proposed for each stage of the vertical chain of power distribution TSV pairs. A mathematical model for tradeoff between TSV resistance and amount of decoupling capacitance on each DRAM die is proposed for a 3D-DRAM-Over-Logic system. The models are developed by following a three step approach: 1) design physical model, 2) convert it to equivalent electrical model, and 3) formulate the mathematical model based on the electrical model. The accuracy, speed and memory requirement of the proposed mathematical model is compared with equivalent Ansoft Nexxim models.
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| 2. |
- Ahsan, Naveed, 1974-
(författare)
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Reconfigurable and Broadband Circuits for Flexible RF Front Ends
- 2009
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Most of today’s microwave circuits are designed for specific function and special need. There is a growing trend to have flexible and reconfigurable circuits. Circuits that can be digitally programmed to achieve various functions based on specific needs. Realization of high frequency circuit blocks that can be dynamically reconfigured to achieve the desired performance seems to be challenging. However, with recent advances in many areas of technology these demands can now be met.Two concepts have been investigated in this thesis. The initial part presents the feasibility of a flexible and programmable circuit (PROMFA) that can be utilized for multifunctional systems operating at microwave frequencies. Design details and PROMFA implementation is presented. This concept is based on an array of generic cells, which consists of a matrix of analog building blocks that can be dynamically reconfigured. Either each matrix element can be programmed independently or several elements can be programmed collectively to achieve a specific function. The PROMFA circuit can therefore realize more complex functions, such as filters or oscillators. Realization of a flexible RF circuit based on generic cells is a new concept. In order to validate the idea, two test chips have been fabricated. The first chip implementation was carried out in a 0.2μm GaAs process, ED02AH from OMMICTM. The second chip was implemented in a standard 90nm CMOS process. Simulated and measured results are presented along with some key applications such as low noise amplifier, tunable band pass filter and a tunable oscillator.The later part of the thesis covers the design and implementation of broadband RF front-ends that can be utilized for multistandard terminals such as software defined radio (SDR). The concept of low gain, highly linear frontends has been presented. For proof of concept two test chips have been implemented in 90nm CMOS technology process. Simulated and measurement results are presented. These RF front-end implementations utilize wideband designs with active and passive mixer configurations.We have also investigated narrowband tunable LNAs. A dual band tunable LNA MMIC has been fabricated in 0.2μm GaAs process. A self tuning technique has been proposed for the optimization of this LNA.
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| 3. |
- Albertsson, Dagur Ingi
(författare)
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Spintronic and Electronic Oscillators for Magnetic Field Sensing and Ising Machines
- 2023
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Oscillators can exhibit a range of complex dynamics which are often encountered in nature. These characteristics include synchronization, injection locking, chaos, bifurcations, etc. To date, the applications of electronic oscillators has mostly been limited to communication systems. However, in recent years, the possibility of using the rich dynamics of oscillators in unconventional applications, including time-based information processing and computational applications, has been also explored. In this thesis, this potential is investigated using emerging spintronic oscillators and established electronic oscillators. The first part of this thesis targets emerging spintronic oscillators, which exhibit a range of attractive features, including GHz operating frequency, wide tunability and nanoscale size. To explore the potential of these devices, an electrical behavioural model was developed for the promising three-terminal spin-Hall nano-oscillator. The behavioural model is based on the macrospin approximation, which is commonly used to describe the operation principles of spintronic oscillators, and it was implemented in Verilog-A. Moreover, the behavioural model was verified against experimental measurements from literature, demonstrating that the most important characteristics of three-terminal spin-Hall nano-oscillators are accurately captured. Subsequently, two potential applications that could benefit from the unique characteristics of spintronic oscillators were identified and explored. First, a magnetic field sensing system, which takes advantage of the wide frequency tunability of spintronic oscillators as a function of externally applied magnetic field, was proposed and demonstrated. This sensing system, inspired by voltage-controlled oscillator analog-to-digital converters, shows performance similar to the state-of-the-art magnetic field sensors, making it a promising application for spintronic oscillators. Next, the possibility of utilizing spintronic oscillators to realize Ising machines (IMs) was explored and demonstrated with numerical simulations. This was the first-time demonstration of spintronic oscillator-based Ising machines. The numerical simulation results show that spintronic oscillators are a promising device to realize ultra-fast Ising Machines able to solve complex combinatorial optimization problems on nano-second time scale.The second part of the thesis extends on the idea of oscillator-based IMs, but using electronic oscillators. The potential of realizing highly reconfigurable oscillator-based IMs based on quasiperiodically modulated coupling was explored. The advantages and potential challenges associated with this approach were highlighted, and a proof-of-concept IM using CMOS ring oscillators was proposed and simulated. Finally, a completely new type of IMs based on bifurcations in a network of coupled Duffing oscillators was proposed and developed. This work highlights a new research direction based on using dynamical systems implemented with analog circuits to realize IMs.
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| 4. |
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| 5. |
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| 6. |
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| 7. |
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| 8. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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A Low-Leakage Dynamic Multi-Ported Register file in 0.13mm CMOS
- 2001
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Ingår i: ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design. - New York, USA : ACM. - 1581133715 ; , s. 68-71
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Konferensbidrag (refereegranskat)abstract
- Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256X32b 4-read/write-port Register-File for ~6GHz operation at 1.2V in a 0.13 utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned remains are able to improve upon all-low-Vt performance by 4%, while maintaining Dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5X.
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| 9. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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A sub-130-nm conditional keeper technique
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 37:5, s. 633-638
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Tidskriftsartikel (refereegranskat)abstract
- Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction
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| 10. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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A Wire Capacitance Estimation Technique for Power Consuming Interconnections at High Levels of Abstraction
- 1997
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Ingår i: In proceedings of: International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS. ; , s. 305-314
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Konferensbidrag (refereegranskat)abstract
- A new wire estimation technique is presented. It utilizes the topology of the netlist and is sensitive to the actual design. It has the unique quality to estimate the length of every power consuming interconnection individually. Compared to other wire length estimation techniques which use average or total wire length, the result of the new technique shows a strong correlation with the result of "real" automatic placement and route tools. Hence it can estimate a reasonable wire capacitance for each interconnection. The individual wire lengths, combined with individual node activities, are essential for an accurate power estimation.
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| 11. |
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| 12. |
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| 13. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Conditional burn-in keeper for dynamic circuits
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A dynamic circuit with a conditional keeper for burn-in. In the described embodiments, a conditional keeper is provided which is active only during the burn-in test, where the conditional keeper is sized larger than the standard keepers so as to compensate for additional leakage currents in the dynamic circuit.
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| 14. |
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| 15. |
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| 16. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Differential charge transfer sense ampliifier
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A sense amplifier for reading memory cells in a SRAM, the sense amplifier comprising two gate-biased pMOSFETs, each corresponding to a selected bitline. The gates of the two gate-biased pMOSFETs have their gates biased to a bias voltage, their sources coupled to the selected bitlines via column-select transistors, and their drains coupled via pass transistors to the two ports of two cross-coupled inverters, the cross-coupled inverters forming a latch. After a selected bitline pair has been pre-charged and the pre-charge phase ends, one of the two gate-biased pMOSFETs quickly goes into its subthreshold region as one of the bitlines discharges through its corresponding memory cell, thereby cutting off the bitline's capacitance from the sense amplifier. When the pass transistors are enabled, the other of the two pMOSFETs allows a significant bitline charge to transfer via its corresponding pass transistor to its corresponding port, whereas a relatively much smaller charge is transferred to the other port. This charge transfer scheme allows a differential voltage to quickly develop at the ports, thereby providing a fast latch and read operation with reduced power consumption. Bitline voltage swing may also be reduced to reduce power consumption.
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| 17. |
- Alvandpour, Atila, 1960-
(författare)
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Domino circuit
- 2002
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Patent (populärvet., debatt m.m.)abstract
- A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage lin
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| 18. |
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| 19. |
- Alvandpour, Atila, 1960-
(författare)
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Enhanced domino circuit
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A domino logic circuit contained within an integrated circuit includes a dynamic logic circuit and an intermediate logic circuit. The intermediate logic circuit includes a pull-up transistor having a source terminal coupled to a source voltage line and an n-block transistor having a source terminal connected to a low ground voltage line.
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| 20. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Fast dual-rail dynamic logic style
- 2005
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Patent (populärvet., debatt m.m.)abstract
- A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
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| 21. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Fast static receiver with input dependent inversion threshold.
- 2006
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Patent (populärvet., debatt m.m.)abstract
- A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.
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| 22. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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Flash (II)-Domino : a fast dual-rail dynamic logic style
- 2004
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Patent (populärvet., debatt m.m.)abstract
- A dual-rail static logic gate with a self cut-off mechanism is disclosed. In an embodiment, the output of the first rail is coupled to the input of the pull-up device of the second rail and vice versa. The cross-coupling allows the self cut-off mechanism of the static gate to function properly and provides for components which have lower capacitance than conventional static gates. The lower capacitance results in a faster static gate.
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| 23. |
- Alvandpour, Atila, 1960-, et al.
(författare)
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GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering
- 2000
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Ingår i: In proceedings of: IEEE International Symposium on Circuits and Systems. Vol.5. - : IEEE. - 0780354826 ; , s. 465-468
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Konferensbidrag (refereegranskat)abstract
- In this paper, interconnection length estimation is discussed and a general, simple, fast and efficient estimation technique is proposed. In contrast to traditional average length estimation techniques, such as the one based on Rent's rule, the new technique utilizes the topological information of the actual netlist and estimates the length of each interconnection separately. The result of the estimation can be directly used to assign a reasonable R and C to each interconnect, including long and wide buses. Consequently, the new technique enhances the accuracy of power and delay estimations at higher design levels of abstraction
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