| 1. |
- Czernohorsky, M., et al.
(författare)
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Stability of crystalline Gd(2)O(3) thin films on silicon during rapid thermal annealing
- 2008
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Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 23:3, s. 035010-
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd(2)O(3) layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack ( silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 degrees C anneal.
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| 2. |
- Lemme, Max C., 1970-, et al.
(författare)
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Complementary metal oxide semiconductor integration of epitaxial Gd(2)O(3)
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:1, s. 258-261
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, epitaxial gadolinium oxide (Gd(2)O(3)) is reviewed as a potential high-K gate dielectric, both "as deposited" by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a "gentle" replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd(2)O(3) gate dielectrics is explored by carefully controlling the annealing conditions.
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| 3. |
- Efavi, J K, et al.
(författare)
-
Investigation of NiAlN as gate-material for submicron CMOS technology
- 2004
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 76:1-4, s. 354-359
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Tidskriftsartikel (refereegranskat)abstract
- Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.
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| 4. |
- Gottlob, H. D. B., et al.
(författare)
-
0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
- 2006
-
Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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| 5. |
- Gottlob, H. D. B., et al.
(författare)
-
CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
- 2006
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
-
Tidskriftsartikel (refereegranskat)abstract
- Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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| 6. |
- Gottlob, H. D. B., et al.
(författare)
-
Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
-
Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
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Tidskriftsartikel (refereegranskat)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
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| 7. |
- Gottlob, H. D. B., et al.
(författare)
-
Gentle FUSI NiSi metal gate process for high-k dielectric screening
- 2008
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 85:10, s. 2019-2021
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).
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| 8. |
- Gottlob, H. D. B., et al.
(författare)
-
Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
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| 9. |
- Hurley, P. K., et al.
(författare)
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Interface defects in HfO2, LaSiOx, and Gd2O3 high-k/metal-gate structures on silicon
- 2008
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Ingår i: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 155:2, s. G13-G20
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Tidskriftsartikel (refereegranskat)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.
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| 10. |
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| 11. |
- Wahlbrink, T., et al.
(författare)
-
Highly selective etch process for silicon-on-insulator nano-devices
- 2005
-
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 78-79:SI, s. 212-217
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Tidskriftsartikel (refereegranskat)abstract
- Reactive ion etch (RIE) processes with HBr/O-2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12 nm gate length and optimized photonic devices with ultrahigh Q-factors.
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| 12. |
- Echtermeyer, T., et al.
(författare)
-
Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes
- 2007
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621
-
Tidskriftsartikel (refereegranskat)abstract
- Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
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| 13. |
- Efavi, J K, et al.
(författare)
-
Tungsten work function engineering for dual metal gate nano-CMOS
- 2005
-
Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 16:7, s. 433-436
-
Tidskriftsartikel (refereegranskat)abstract
- A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.
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| 14. |
- Emmel, M., et al.
(författare)
-
Electronic properties of Co2FeSi investigated by X-ray magnetic linear dichroism
- 2014
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Ingår i: Journal of Magnetism and Magnetic Materials. - : Elsevier BV. - 0304-8853 .- 1873-4766. ; 368, s. 364-373
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Tidskriftsartikel (refereegranskat)abstract
- We present experimental XMLD spectra measured on epitaxial (001)-oriented thin Co2FeSi films, which are rich in features and depend sensitively on the degree of atomic order and interdiffusion from capping layers. Al- and Cr-capped films with different degrees of atomic order were prepared by DC magnetron sputtering by varying the deposition temperatures. The local structural properties of the film samples were additionally investigated by nuclear magnetic resonance (NMR) measurements. The XMLD spectra of the different samples show clear and uniform trends at the L-3,L-2 edges. The Al-capped samples show similar behavior as previous measured XMLD spectra of Co2FeSi0.6Al0.4. Thus, we assume that during deposition Al atoms are being implanted into the subsurface of Co2FeSi. Such an interdiffusion is not observed for the corresponding Cr-capped films, which makes Cr the material of choice for capping Co2FeSi films. We report stronger XMLD intensities at the L-3,L-2 Co and Fe egdes for films with a higher saturation magnetization. Additionally, we compare the spectra with ab initio predictions and obtain a reasonably good agreement. Furthermore, we were able to detect an XMCD signal at the Si Ledge, indicating the presence of a magnetic moment at the Si atoms.
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| 15. |
- Engstrom, O., et al.
(författare)
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Navigation aids in the search for future high-k dielectrics : Physical and electrical trends
- 2007
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 622-626
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Tidskriftsartikel (refereegranskat)abstract
- From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.
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| 16. |
- Fuchs, A., et al.
(författare)
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Nanowire fin field effect transistors via UV-based nanoimprint lithography
- 2006
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:6, s. 2964-2967
-
Tidskriftsartikel (refereegranskat)abstract
- A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3 sigma). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.
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| 17. |
- Gottlob, H. D. B., et al.
(författare)
-
Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics
- 2006
-
Ingår i: ESSDERC 2006. - 9781424403011 ; , s. 150-153
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Konferensbidrag (refereegranskat)abstract
- Two process concepts for integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
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| 18. |
- Gottlob, H D B, et al.
(författare)
-
Introduction of crystalline high-k gate dielectrics in a CMOS process
- 2005
-
Ingår i: Journal of Non-Crystalline Solids. - : Elsevier BV. - 0022-3093 .- 1873-4812. ; 351:21-23, s. 1885-1889
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Tidskriftsartikel (refereegranskat)abstract
- In this work we report on methods to introduce crystalline rare-earth (RE) oxides with high (k > 3.9) dielectric constants (high-k) in a CMOS process flow. Key process steps compatible with crystalline praseodymium oxide (Pr2O3) high-k gate dielectric have been developed and evaluated in metal-oxide-semiconductor (MOS) structures and n-MOS transistors fabricated in an adapted conventional bulk process. From capacitance-voltage measurements a dielectric constant of k = 36 has been calculated. Furthermore an alternative process sequence suitable for the introduction of high-k material into silicon on insulator (SOI) MOS-field-effect-transistors (MOSFET) is presented. The feasibility of this process is shown by realization of n- and p-MOSFETs with standard SiO2 gate dielectric as demonstrator. SiO2 gate dielectric can be replaced by crystalline RE-oxides in the next batch fabrication.
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| 19. |
- Gottlob, H. D. B., et al.
(författare)
-
Investigation of high-K gate stacks with epitaxial Gd(2)O(3) and FUSINiSi metal gates down to CET=0.86 nm
- 2006
-
Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 9:6, s. 904-908
-
Tidskriftsartikel (refereegranskat)abstract
- Novel gate stacks with epitaxial gadoliniurn oxide (Gd(2)O(3)) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10(-7) A cm(-2) are observed at a capacitance equivalent oxide thickness of CET = 1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd(2)O(3) thickness of 3.1 nm yield current densities down to 0.5 A cm(-2) at V(g) = + 1 V. The extracted dielectric constant for these gate stacks ranges from k = 13 to 14. These results emphasize the potential of NiSi/Gd(2)O(3) gate stacks for future material-based scaling of CMOS technology.
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| 20. |
- Gottlob, H. D. B., et al.
(författare)
-
Leakage current mechanisms in epitaxial Gd(2)O(3) high-k gate dielectrics
- 2008
-
Ingår i: Electrochemical and solid-state letters. - : The Electrochemical Society. - 1099-0062 .- 1944-8775. ; 11:3, s. G12-G14
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Tidskriftsartikel (refereegranskat)abstract
- We report on leakage current mechanisms in epitaxial gadolinium oxide (Gd(2)O(3)) high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semi con doctor capacitors are gated with complementary-metal-oxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd(2)O(3) thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of Phi(T) = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction.
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| 21. |
- Gottlob, H D B, et al.
(författare)
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Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics
- 2006
-
Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:2, s. 710-714
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Tidskriftsartikel (refereegranskat)abstract
- A "gate first" silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10 mu m down to 40 nm on a fully depleted 25 nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100 nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxial high-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.
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| 22. |
- Hurley, P.K., et al.
(författare)
-
Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/MetalGate Structures on Silicon
- 2008
-
Ingår i: J. Electrochem. Soc.. ; 155:2, s. G13-G20
-
Tidskriftsartikel (refereegranskat)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.
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| 23. |
- Lemme, Max C., 1970-, et al.
(författare)
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Comparison of metal gate electrodes on MOCVD HfO2
- 2005
-
Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 45:5-6, s. 953-956
-
Tidskriftsartikel (refereegranskat)abstract
- Metal gate electrodes of sputtered aluminum (At), titanium nitride (TiN) and nickel aluminum nitride (NiAlN) are investigated in this work. They are compared with respect to their compatibility with metal organic chemical vapor deposited (MOCVD) hafnium dioxide (HfO2) gate dielectrics. TiN, with a midgap work function of 4.65 eV on SiO2, exhibits promising characteristics as metal gate on HfO2. In addition, encouraging results are presented for the ternary metal NiAlN, whereas classic At electrodes are found unstable in conjunction with HfO2.
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| 24. |
- Lemme, Max C., 1970-, et al.
(författare)
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Nanoscale TiN metal gate technology for CMOS integration
- 2006
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1551-1554
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Tidskriftsartikel (refereegranskat)abstract
- A TiN metal gate technology including essential natiostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 degrees C and yield excellent CV and IV characteristics.
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| 25. |
- Lemme, Max C., 1970-, et al.
(författare)
-
Non-planar devices for nanoscale CMOS
- 2007
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Ingår i: Nanoscaled Semiconductor-on-Insulator Structures and Devices. - Dordrecht : Springer Netherlands. - 9781402063787 ; , s. 19-32
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Konferensbidrag (refereegranskat)abstract
- In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and rnanufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.
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