| 1. |
|
|
| 2. |
- Momozawa, Y, et al.
(författare)
-
IBD risk loci are enriched in multigenic regulatory modules encompassing putative causative genes
- 2018
-
Ingår i: Nature communications. - : Springer Science and Business Media LLC. - 2041-1723. ; 9:1, s. 2427-
-
Tidskriftsartikel (refereegranskat)abstract
- GWAS have identified >200 risk loci for Inflammatory Bowel Disease (IBD). The majority of disease associations are known to be driven by regulatory variants. To identify the putative causative genes that are perturbed by these variants, we generate a large transcriptome data set (nine disease-relevant cell types) and identify 23,650 cis-eQTL. We show that these are determined by ∼9720 regulatory modules, of which ∼3000 operate in multiple tissues and ∼970 on multiple genes. We identify regulatory modules that drive the disease association for 63 of the 200 risk loci, and show that these are enriched in multigenic modules. Based on these analyses, we resequence 45 of the corresponding 100 candidate genes in 6600 Crohn disease (CD) cases and 5500 controls, and show with burden tests that they include likely causative genes. Our analyses indicate that ≥10-fold larger sample sizes will be required to demonstrate the causality of individual genes using this approach.
|
|
| 3. |
|
|
| 4. |
|
|
| 5. |
|
|
| 6. |
|
|
| 7. |
- Gottlob, H. D. B., et al.
(författare)
-
Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
-
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
-
Tidskriftsartikel (refereegranskat)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
|
|
| 8. |
- Liu, Jimmy Z, et al.
(författare)
-
Dense genotyping of immune-related disease regions identifies nine new risk loci for primary sclerosing cholangitis.
- 2013
-
Ingår i: Nature genetics. - : Springer Science and Business Media LLC. - 1546-1718 .- 1061-4036. ; 45:6, s. 670-5
-
Tidskriftsartikel (refereegranskat)abstract
- Primary sclerosing cholangitis (PSC) is a severe liver disease of unknown etiology leading to fibrotic destruction of the bile ducts and ultimately to the need for liver transplantation. We compared 3,789 PSC cases of European ancestry to 25,079 population controls across 130,422 SNPs genotyped using the Immunochip. We identified 12 genome-wide significant associations outside the human leukocyte antigen (HLA) complex, 9 of which were new, increasing the number of known PSC risk loci to 16. Despite comorbidity with inflammatory bowel disease (IBD) in 72% of the cases, 6 of the 12 loci showed significantly stronger association with PSC than with IBD, suggesting overlapping yet distinct genetic architectures for these two diseases. We incorporated association statistics from 7 diseases clinically occurring with PSC in the analysis and found suggestive evidence for 33 additional pleiotropic PSC risk loci. Together with network analyses, these findings add to the genetic risk map of PSC and expand on the relationship between PSC and other immune-mediated diseases.
|
|
| 9. |
- Gottlob, H. D. B., et al.
(författare)
-
Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
-
Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
-
Tidskriftsartikel (refereegranskat)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
|
|
| 10. |
|
|
| 11. |
|
|
| 12. |
|
|
| 13. |
|
|
| 14. |
- Chiesa, Marco, 1987-, et al.
(författare)
-
On the resiliency of randomized routing against multiple edge failures
- 2016
-
Ingår i: 43rd International Colloquium on Automata, Languages, and Programming, ICALP 2016. - : Schloss Dagstuhl- Leibniz-Zentrum fur Informatik GmbH, Dagstuhl Publishing. - 9783959770132
-
Konferensbidrag (refereegranskat)abstract
- We study the Static-Routing-Resiliency problem, motivated by routing on the Internet: Given a graph G = (V, E), a unique destination vertex d, and an integer constant c > 0, does there exist a static and destination-based routing scheme such that the correct delivery of packets from any source s to the destination d is guaranteed so long as (1) no more than c edges fail and (2) there exists a physical path from s to d? We embark upon a study of this problem by relating the edge-connectivity of a graph, i.e., the minimum number of edges whose deletion partitions G, to its resiliency. Following the success of randomized routing algorithms in dealing with a variety of problems (e.g., Valiant load balancing in the network design problem), we embark upon a study of randomized routing algorithms for the Static-Routing-Resiliency problem. For any k-connected graph, we show a surprisingly simple randomized algorithm that has expected number of hops O(|V|k) if at most k-1 edges fail, which reduces to O(|V|) if only a fraction t of the links fail (where t < 1 is a constant). Furthermore, our algorithm is deterministic if the routing does not encounter any failed link.
|
|
| 15. |
- Chiesa, Marco, 1987-, et al.
(författare)
-
On the Resiliency of Static Forwarding Tables
- 2017
-
Ingår i: IEEE/ACM Transactions on Networking. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-6692 .- 1558-2566. ; 25:2, s. 1133-1146
-
Tidskriftsartikel (refereegranskat)abstract
- Fast reroute and other forms of immediate failover have long been used to recover from certain classes of failures without invoking the network control plane. While the set of such techniques is growing, the level of resiliency to failures that this approach can provide is not adequately understood. In this paper, we embarked upon a systematic algorithmic study of the resiliency of forwarding tables in a variety of models (i.e., deterministic/probabilistic routing, with packet-headerrewriting, with packet-duplication). Our results show that the resiliency of a routing scheme depends on the "connectivity" k of a network, i.e., the minimum number of link deletions that partition a network. We complement our theoretical result with extensive simulations. We show that resiliency to four simultaneous link failures, with limited path stretch, can be achieved without any packet modification/duplication or randomization. Furthermore, our routing schemes provide resiliency against k - 1 failures, with limited path stretch, by storing log(k) bits in the packet header, with limited packet duplication, or with randomized forwarding technique.
|
|
| 16. |
- Chiesa, Marco, 1987-, et al.
(författare)
-
The quest for resilient (static) forwarding tables
- 2016
-
Ingår i: INFOCOM 2016 - The 35th Annual IEEE International Conference on Computer Communications, IEEE. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467399531
-
Konferensbidrag (refereegranskat)abstract
- Fast Reroute (FRR) and other forms of immediate failover have long been used to recover from certain classes of failures without invoking the network control plane. While the set of such techniques is growing, the level of resiliency to failures that this approach can provide is not adequately understood. We embark upon a systematic algorithmic study of the resiliency of immediate failover in a variety of models (with/without packet marking/duplication, etc.). We leverage our findings to devise new schemes for immediate failover and show, both theoretically and experimentally, that these outperform existing approaches.
|
|
| 17. |
|
|
| 18. |
|
|
| 19. |
- Engström, Olof, 1943, et al.
(författare)
-
Gate stacks
- 2013
-
Ingår i: Nanoscale CMOS: Innovative Materials, Modeling and Characterization. - : Wiley. ; , s. 23 - 67
-
Bokkapitel (övrigt vetenskapligt/konstnärligt)
|
|
| 20. |
- Engström, Olof, 1943, et al.
(författare)
-
Internal photoemission technique for high-k oxide/semiconductor band offset determination: The influence of semiconductor bulk properties
- 2014
-
Ingår i: 44th European Solid-State Device Research Conference, ESSDERC 2014, Palazzo del CasinoVenezia Lido, Italy, 22-26 September 2014. - 1930-8876. - 9781479943784 ; , s. 369-372
-
Konferensbidrag (refereegranskat)abstract
- A method for extracting energy band alignment of metal/high-k oxide/semiconductor structures from internal photoemission experiments is discussed by modeling the excitation and relaxation processes taking place in the semiconductor at photon irradiation. Classical literature data on photoemission of electrons from silicon and germanium surfaces into vacuum is compared with more recently published data on HfO2/Si and HfO2/Ge structures to identify characteristic features of photoelectric yield. We find that a dominating structure of such spectra, which often has been assumed to originate from the oxide barrier, derives from the energy dependence of absorption coefficient and mean free paths of excited electrons. Our results indicate that most IPE data on high-k oxide/silicon and germanium structures need re-interpretation.
|
|
| 21. |
- Lu, Y., et al.
(författare)
-
Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors
- 2009
-
Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 352-355
-
Tidskriftsartikel (refereegranskat)abstract
- With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.
|
|
| 22. |
- Mitrovic, I. Z., et al.
(författare)
-
Atomic-layer deposited thulium oxide as a passivation layer on germanium
- 2015
-
Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 117:21
-
Tidskriftsartikel (refereegranskat)abstract
- A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05±0.2eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77eV with an apparent Urbach tail signifying band gap tailing at ∼5.3eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3eV) and electrons (∼2eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge.
|
|
| 23. |
- Mitrovic, I. Z., et al.
(författare)
-
Interface engineering of Ge using thulium oxide : Band line-up study
- 2013
-
Ingår i: Microelectronic Engineering. - : Elsevier. - 0167-9317 .- 1873-5568. ; 109, s. 204-207
-
Tidskriftsartikel (refereegranskat)abstract
- This paper investigates the band line-up and optical properties (dielectric function) of Tm2O3/Ge gate stacks deposited by atomic layer deposition. X-ray photoelectron spectroscopy has been performed to ascertain the shallow core levels (Ge3d and Tm4d) in ultra-thin and bulk Tm2O3/Ge stacks as well as valence band maxima in Ge and bulk Tm2O3. The valence band offset of Tm2O3/Ge has been found to be 2.95 +/- 0.08 eV. Vacuum ultra violet variable angle spectroscopic ellipsometry studies reveal the indirect band gap nature of Tm2O3, with the value extracted from the Tauc method of 5.3 +/- 0.1 eV. A distinct absorption feature is observed at similar to 3.2 eV below the band gap of Tm2O3, and clearly distinguished from the Si and Ge critical points. A dielectric constant of 14 to 15 has been derived from the electrical measurements on 5 nm Tm2O3/epi Ge/Si gate stacks. The band line-up study of Tm2O3/Ge implies an acceptable barrier for holes (2.95 eV) and electrons (greater than 1.7 eV) for Ge MOSFET engineering.
|
|
| 24. |
- Mitrovic, I. Z., et al.
(författare)
-
Interface engineering routes for a future cmos ge-based technology
- 2014
-
Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; , s. 73-88
-
Konferensbidrag (refereegranskat)abstract
- We present an overview study of two germanium interface engineering routes, firstly a germanate formation via La2O3 and Y2O3, and secondly a barrier layer approach using Al2O3 and Tm2O3. The interfacial composition, uniformity, thickness, band gap, crystallinity, absorption features and valence band offset are determined using X-ray photoelectron spectroscopy, ultra violet variable angle spectroscopic ellipsometry, and high resolution transmission electron microscopy. The correlation of these results with electrical characterization data make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS.
|
|
| 25. |
- Mitrovic, I. Z., et al.
(författare)
-
On the nature of the interfacial layer in ultra-thin TiN/LaluO3 gate stacks
- 2012
-
Ingår i: Journal of Applied Physics. - : AIP Publishing. - 0021-8979 .- 1089-7550. ; 112:4, s. 044102-
-
Tidskriftsartikel (refereegranskat)abstract
- We present a detailed investigation on the nature of the interfacial layer (IL) in ultra-thin TiN/LaLuO3 (LLO) gate stacks, which is of importance to facilitate CMOS scaling. The molecular beam deposited LaLuO3 films are found to be amorphous by high-resolution transmission electron microscopy. A similar to 9 angstrom thick LaLuO3/interlayer transition observed by medium energy ion scattering correlates with the presence of a dual silicate/SiO2-like interfacial layer derived from the analysis of photoelectron line positions and electron energy loss spectra. A theoretical model is used for the dielectric transition in a bi-layer LaLuO3/IL structure, linking physical and electrical characterization data. The obtained leakage current of 10(-3) A/cm(2) at 1.5 V and equivalent oxide thickness of 0.75 nm for TiN/LaLuO3 gate stacks are adequate for scaling in the 14-12 nm node.
|
|
