| 1. |
- Attaran, A., et al.
(författare)
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CMOS class AB power amplifier linearization by feed forward technique for wireless communications
- 2011
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Ingår i: International Journal on Communications Antenna and Propagation. - 2039-5086. ; 1:1, s. 29-33
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a class AB PA with an optimized load impedance for maximum output power in a standard 180 nm CMOS technology. This Amplifier shows a measured output power of 22.36 dBm at 2.4 GHz for a supply voltage of 1.8 V. It will display necessary trade offs for optimum output power and small signal gain. Simulation results show that the drain efficiency at 1 dB compression point reaches 31.41%. Additionally, using a feed forward linearization technique, P1-dB is increased to 24.05 dBm which shows 3.46 dB improvement compared to the case without linearization. Enhancement in the amplifier linearity range leads to lower adjacent channel interference and thus higher data transfer rate.
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| 2. |
- Razzaghpour, Milad, et al.
(författare)
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A Highly-Accurate Low-Power CMOS Potentiostat for Implantable BioSensors
- 2011
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Ingår i: Biomedical Circuits and Systems Conference (BioCAS), 2011 IEEE. - 9781457714696 ; , s. 5-8
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Konferensbidrag (refereegranskat)abstract
- Current-mirror-based potentiostats suffer from sys-tematic and random errors causing offset, gain and linearityerror in reading out the sensor data. In this work, a newpotentiostat topology is proposed to eliminate the systematicerror via an error-cancellation loop. The loop takes advantageof an error-tracking amplifier connected to a transimpedanceamplifier with adjustable input common-mode voltage. Due tothe enhanced loop gain, the potentiostat is able to accuratelycopy the sensor current which will then be converted into theproportional voltage. Additionally, a theoretical discussion ofthe proposed topology is given and a thorough study on theeffect of random error sources is carried out. The potentiostat isdesigned and simulated in a 150nm CMOS process. The resultsverify a highly-linear highly-accurate performance in a low-noisecondition, while consuming only 32 μW.
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| 3. |
- Razzaghpour, Milad, et al.
(författare)
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Analog circuit optimization via a modified Imperialist Competitive Algorithm
- 2011
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Ingår i: 2011 IEEE International Symposium on Circuits and Systems (ISCAS). - : IEEE conference proceedings. - 9781424494729 - 9781424494736 ; , s. 2273-2276
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Konferensbidrag (refereegranskat)abstract
- This paper proposes a novel evolutionary approach based on a modified Imperialist Competitive Algorithm for analog circuit design optimization. The original Imperialist Competitive Algorithm shows a low search ability in high-dimensional search spaces which is the case in optimization of analog circuits. The proposed tool addresses this problem by introducing a society-based algorithm with novel “selection” and “movement” operators. The tool is also equipped with a “mutation” operator increasing the search ability. A multi-dimensional analog design problem along with a mathematical benchmark are used to demonstrate its capability. Moreover, a thorough comparison between the original Imperialist Competitive Algorithm, the proposed algorithm and genetic algorithm as a reference is carried out. It will be revealed that the proposed algorithm is capable of exploring the cost space more efficiently resulting in better trade-offs between design objectives to reach better cost values. Additionally, the proposed algorithm is faster than the other under-test algorithms which is a key feature in simulation-based optimization procedures.
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