| 1. |
- Albertsson, Dagur Ingi, et al.
(författare)
-
A Magnetic Field-to-Digital Converter Employing a Spin-Torque Nano-Oscillator
- 2020
-
Ingår i: IEEE transactions on nanotechnology. - : Institute of Electrical and Electronics Engineers (IEEE). - 1536-125X .- 1941-0085. ; 19, s. 565-570
-
Tidskriftsartikel (refereegranskat)abstract
- In this work, a novel magnetic field-to-digital converter based on emerging spin-torque nano-oscillators (STNOs) is proposed. The architecture is inspired by voltage controlled oscillator (VCO)-based analog-to-digital converters (ADCs) which have shown inherent first-order noise shaping of both quantization- and phase-noise without the need for feedback. In the proposed architecture, the STNO acts both as a magnetic field sensor and VCO. The architecture's performance is evaluated in terms of signal-to-noise and distortion ratio (SNDR) utilizing Verilog-AMS modeling, where a macrospin model fitted to experimental data is employed for accurate description of the STNO operation. The presented simulation results demonstrate the potential of the STNO-based magnetic field-to-digital converter architecture.
|
|
| 2. |
- Albertsson, Dagur Ingi, 1993-, et al.
(författare)
-
Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators
- 2019
-
Ingår i: IEEE transactions on magnetics. - : IEEE Press. - 0018-9464 .- 1941-0069. ; 55:10
-
Tidskriftsartikel (refereegranskat)abstract
- Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.
|
|
| 3. |
- Albertsson, Dagur Ingi, et al.
(författare)
-
Experimental Demonstration of Duffing Oscillator-Based Analog Ising Machines
- 2024
-
Ingår i: LASCAS 2024 - 15th IEEE Latin American Symposium on Circuits and Systems, Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a proof-of-concept analog Ising Machine, which can solve combinatorial optimization problems using bifurcations in networks of coupled Duffing oscillators. The proof-of-concept system consists of a network of four coupled Duffing oscillators implemented with low-cost components on a prototyping board. Experimental results demonstrate that the proposed prototype operates as an Ising Machine and it can solve various Max-Cut problems. This work provides the foundation towards realizing analog Ising Machines based on circuits that exhibit bifurcation properties, such as the Duffing oscillators, and that can be scaled to large networks.
|
|
| 4. |
- Albertsson, Dagur Ingi, et al.
(författare)
-
Highly reconfigurable oscillator-based Ising Machine through quasiperiodic modulation of coupling strength
- 2023
-
Ingår i: Scientific Reports. - : Springer Nature. - 2045-2322. ; 13:1
-
Tidskriftsartikel (refereegranskat)abstract
- Ising Machines (IMs) have the potential to outperform conventional Von-Neuman architectures in notoriously difficult optimization problems. Various IM implementations have been proposed based on quantum, optical, digital and analog CMOS, as well as emerging technologies. Networks of coupled electronic oscillators have recently been shown to exhibit characteristics required for implementing IMs. However, for this approach to successfully solve complex optimization problems, a highly reconfigurable implementation is needed. In this work, the possibility of implementing highly reconfigurable oscillator-based IMs is explored. An implementation based on quasiperiodically modulated coupling strength through a common medium is proposed and its potential is demonstrated through numerical simulations. Moreover, a proof-of-concept implementation based on CMOS coupled ring oscillators is proposed and its functionality is demonstrated. Simulation results show that our proposed architecture can consistently find the Max-Cut solution and demonstrate the potential to greatly simplify the physical implementation of highly reconfigurable oscillator-based IMs.
|
|
| 5. |
- Albertsson, Dagur Ingi, et al.
(författare)
-
Ising Machine Based on Bifurcations in a Network of Duffing Oscillators
- 2023
-
Ingår i: Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- Ising Machines have been extensively explored latelyfor developing new nonconventional computing architectures. Arecently proposed approach, based on simulating a dynamicalsystem exhibiting bifurcations, has shown promising performance. Inspired by this concept, we propose using bifurcationsin a network of coupled electrical Duffing oscillators to realize anIsing Machine. Numerical simulations of large Duffing oscillatornetworks, solving various Max-Cut problems, demonstrate thepotential of our proposed approach for realizing Ising Machinesbased on bifurcations. It also establishes a new direction towardsanalog Ising Machine architectures.
|
|
| 6. |
- Albertsson, Dagur Ingi
(författare)
-
Spintronic and Electronic Oscillators for Magnetic Field Sensing and Ising Machines
- 2023
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Oscillators can exhibit a range of complex dynamics which are often encountered in nature. These characteristics include synchronization, injection locking, chaos, bifurcations, etc. To date, the applications of electronic oscillators has mostly been limited to communication systems. However, in recent years, the possibility of using the rich dynamics of oscillators in unconventional applications, including time-based information processing and computational applications, has been also explored. In this thesis, this potential is investigated using emerging spintronic oscillators and established electronic oscillators. The first part of this thesis targets emerging spintronic oscillators, which exhibit a range of attractive features, including GHz operating frequency, wide tunability and nanoscale size. To explore the potential of these devices, an electrical behavioural model was developed for the promising three-terminal spin-Hall nano-oscillator. The behavioural model is based on the macrospin approximation, which is commonly used to describe the operation principles of spintronic oscillators, and it was implemented in Verilog-A. Moreover, the behavioural model was verified against experimental measurements from literature, demonstrating that the most important characteristics of three-terminal spin-Hall nano-oscillators are accurately captured. Subsequently, two potential applications that could benefit from the unique characteristics of spintronic oscillators were identified and explored. First, a magnetic field sensing system, which takes advantage of the wide frequency tunability of spintronic oscillators as a function of externally applied magnetic field, was proposed and demonstrated. This sensing system, inspired by voltage-controlled oscillator analog-to-digital converters, shows performance similar to the state-of-the-art magnetic field sensors, making it a promising application for spintronic oscillators. Next, the possibility of utilizing spintronic oscillators to realize Ising machines (IMs) was explored and demonstrated with numerical simulations. This was the first-time demonstration of spintronic oscillator-based Ising machines. The numerical simulation results show that spintronic oscillators are a promising device to realize ultra-fast Ising Machines able to solve complex combinatorial optimization problems on nano-second time scale.The second part of the thesis extends on the idea of oscillator-based IMs, but using electronic oscillators. The potential of realizing highly reconfigurable oscillator-based IMs based on quasiperiodically modulated coupling was explored. The advantages and potential challenges associated with this approach were highlighted, and a proof-of-concept IM using CMOS ring oscillators was proposed and simulated. Finally, a completely new type of IMs based on bifurcations in a network of coupled Duffing oscillators was proposed and developed. This work highlights a new research direction based on using dynamical systems implemented with analog circuits to realize IMs.
|
|
| 7. |
- Albertsson, Dagur Ingi, et al.
(författare)
-
Ultrafast Ising Machines using spin torque nano-oscillators
- 2021
-
Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 118:11
-
Tidskriftsartikel (refereegranskat)abstract
- Combinatorial optimization problems are known for being particularly hard to solve on traditional von Neumann architectures. This has led to the development of Ising Machines (IMs) based on quantum annealers and optical and electronic oscillators, demonstrating speed-ups compared to central processing unit (CPU) and graphics processing unit (GPU) algorithms. Spin torque nano-oscillators (STNOs) have shown GHz operating frequency, nanoscale size, and nanosecond turn-on time, which would allow their use in ultrafast oscillator-based IMs. Here, we show using numerical simulations based on STNO auto-oscillator theory that STNOs exhibit fundamental characteristics needed to realize IMs, including in-phase/out-of-phase synchronization and second harmonic injection locking phase binarization. Furthermore, we demonstrate numerically that large STNO network IMs can solve Max-Cut problems on nanosecond timescales.
|
|
| 8. |
- Chaourani, Panagiotis, 1989-, et al.
(författare)
-
A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors
- 2018
-
Ingår i: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S). - : IEEE conference proceedings.
-
Konferensbidrag (refereegranskat)abstract
- The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.
|
|
| 9. |
- Chaourani, Panagiotis, 1989-, et al.
(författare)
-
Enabling Area Efficient RF ICs through Monolithic 3D Integration
- 2017
-
Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 610-613
-
Konferensbidrag (refereegranskat)abstract
- The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.
|
|
| 10. |
- Chaourani, Panagiotis, et al.
(författare)
-
Inductors in a Monolithic 3-D Process : Performance Analysis and Design Guidelines
- 2019
-
Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 27:2, s. 468-480
-
Tidskriftsartikel (refereegranskat)abstract
- Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.
|
|
| 11. |
- Chaourani, Panagiotis, 1989-
(författare)
-
Sequential 3D Integration - Design Methodologies and Circuit Techniques
- 2019
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.
|
|
| 12. |
- Chen, Kairang, 1986-
(författare)
-
Energy-Efficient Data Converters for Low-Power Sensors
- 2016
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energy-harvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxide-semiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications.The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-μm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-μm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 μW. Core area of the ADC is 0.679 mm2.The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage capacitive charge pump (CCP) is utilized to achieve the gain-stage instead of using the switch capacitor (SC) amplifier. Unity-gain OTAs have been used as the analog buffers to prevent the charge sharing between the CCP stages. The detailed design considerations are given in this work. The prototype ADC, designed and fabricated in a low-cost 0.35-μm CMOS process, achieves a peak SNDR of 75.6 dB at a sampling rate of 20 kS/s and 76.1 dB at 200 kS/s while consuming 7.68 μW and 96 μW, respectively. The corresponding Schreier FoM are 166.7 dB and 166.3 dB. Since the bandwidth of CCP is tunable, the ADC maintains a SNDR > 75 dB upto 260 kHz. The core area occupied by the ADC is 0.589 mm2.As the low-power sensors might be active only for very short time triggered by an external pulse to acquire the data, the third work is a 14-bit asynchronous two-stage pipelined SAR ADC which has been designed and simulated in 0.18-μm CMOS process. A self-synchronous loop based on an edge detector is utilized to generate an internal clock with variable phase. A tunable delay element enables to allocate the available time for the switch capacitor DACs and the gain-stage. Three separate asynchronous clock generators are implemented to create the control signals for two sub-ADCs and the gain-stage between. Aiming to reduce the power consumption of the gain-stage, simple source followers as the analog buffers are implemented in the 3-stage CCP gain-stage. Post-layout simulation results show that the ADC achieves a SNDR of 83.5 dB while consuming 2.39 μW with a sampling rate of 10 kS/s. The corresponding Schreier FoM is 176.7 dB.
|
|
| 13. |
- Chen, Tingsu, et al.
(författare)
-
A 2 GHz - 8.7 GHz Wideband Balun-LNA with Noise Cancellation and Gain Boosting
- 2012
-
Ingår i: PRIME 2012: Proceedings of the 8th Coference on Ph.D. Research in Microelectronics and Electronics, 2012. - : IEEE conference proceedings. - 9783800734429 ; , s. 59-62
-
Konferensbidrag (refereegranskat)abstract
- A wideband Balun-LNA covering the operation frequency range of magnetic tunnel junction Spin Torque Oscillator is presented. The LNA is a combination of common-source and cross-coupled common-gate stages, which provides wideband matching and noise cancellation, as well as gain boosting. The internal feedback introduced by the cross-coupling allows an additional degree of freedom to select transistor sizes and bias by decoupling the impedance matching, noise, and gain imbalance trade-offs which are present in similar topologies. Two LNAs using the proposed technique are designed in 65nm CMOS. The LNAs have a simulated bandwidth of 2 GHz - 8.7 GHz, gain of 16 dB, IIP3 of -3.5 dBm, and NF < 3.8 dB while consuming 3.72 mW from a 1.2 V power supply.
|
|
| 14. |
- Chen, Tingsu, et al.
(författare)
-
A highly tunable microwave oscillator based on MTJ STO technology
- 2014
-
Ingår i: Microwave and optical technology letters (Print). - : Wiley. - 0895-2477 .- 1098-2760. ; 56:9, s. 2092-2095
-
Tidskriftsartikel (refereegranskat)abstract
- This article presents a fully ESD-protected, highly tunable microwave oscillator based on magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology. The oscillator consists of a compact MTJ STO and a 65 nm CMOS wideband amplifier, which amplifies the RF signal of the MTJ STO to a level that can be used to drive a PLL. The (MTJ STO+amplifier IC) pair shows a measured quality factor (Q) of 170 and a wide tunability range from 3 to 7 GHz, which demonstrate its potential to be used as a microwave oscillator in multiband, multistandard radios.
|
|
| 15. |
- Chen, Tingsu, 1987-, et al.
(författare)
-
An Inductorless Wideband Balun-LNA for Spin Torque Oscillator-based Field Sensing
- 2014
-
Ingår i: Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on. - : IEEE conference proceedings. - 9781479942435 ; , s. 36-39
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a wideband inductorless Balun-LNA targeting spin torque oscillator-based magnetic field sensing applications. The LNA consistsof a CS stage combined with a cross-coupled CG stage, which offers wideband matching, noise/distortion cancellation and gain boosting, simultaneously. The Balun-LNA is implemented in a 65 nm CMOS technology, and it is fully ESD-protected and packaged. Measurement results show a bandwidth of 2 GHz - 7 GHz, a voltage gain of 20 dB, an IIP3 of +2 dBm, and a maximum NF of 5 dB. The LNA consumes 3.84 mW from a 1.2 V power supply and occupies a total silicon area of 0.0044 mm2. The measurement results demonstrate that the proposed Balun-LNA is highly suitable for the STO-based field sensing applications.
|
|
| 16. |
- Chen, Tingsu
(författare)
-
CMOS High Frequency Circuits for Spin Torque Oscillator Technology
- 2014
-
Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively.First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL.The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given.
|
|
| 17. |
- Chen, Tingsu, et al.
(författare)
-
Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I : Analytical Model of the MTJ STO
- 2015
-
Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 62:3, s. 1037-1044
-
Tidskriftsartikel (refereegranskat)abstract
- Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.
|
|
| 18. |
- Chen, Tingsu, et al.
(författare)
-
Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II : Verilog-A Model Implementation
- 2015
-
Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 62:3, s. 1045-1051
-
Tidskriftsartikel (refereegranskat)abstract
- The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.
|
|
| 19. |
- Chen, Tingsu, et al.
(författare)
-
Integration of GMR-based spin torque oscillators and CMOS circuitry
- 2015
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 111, s. 91-99
-
Tidskriftsartikel (refereegranskat)abstract
- This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm(2). The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies. (C) 2015 Elsevier Ltd. All rights reserved.
|
|
| 20. |
- Chen, Tingsu, et al.
(författare)
-
Spin-Torque and Spin-Hall Nano-Oscillators
- 2016
-
Ingår i: Proceedings of the IEEE. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9219 .- 1558-2256. ; 104:10, s. 1919-1945
-
Tidskriftsartikel (refereegranskat)abstract
- This paper reviews the state of the art in spin-torque and spin-Hall-effect-driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.
|
|
| 21. |
- Chen, Tingsu, 1987-, et al.
(författare)
-
Spin-Torque and Spin-Hall Nano-Oscillators
-
Ingår i: Proceedings of the IEEE. - 0018-9219 .- 1558-2256.
-
Tidskriftsartikel (refereegranskat)abstract
- This paper reviews the state of the art in spin-torque and spin Hall effect driven nano-oscillators. After a brief introduction to the underlying physics, the authors discuss different implementations of these oscillators, their functional properties in terms of frequency range, output power, phase noise, and modulation rates, and their inherent propensity for mutual synchronization. Finally, the potential for these oscillators in a wide range of applications, from microwave signal sources and detectors to neuromorphic computation elements, is discussed together with the specific electronic circuitry that has so far been designed to harness this potential.
|
|
| 22. |
- Chen, Tingsu
(författare)
-
Spin Torque Oscillator Modeling, CMOS Design and STO-CMOS Integration
- 2015
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration.An electrical model, which can capture magnetic tunnel junction (MTJ) STO's characteristics, while enabling system- and circuit-level designs and performance evaluations, is of great importance for the development of MTJ STO-based applications. A comprehensive and compact analytical model, which is based on macrospin approximations and can fulfill the aforementioned requirements, is proposed. This model is fully implemented in Verilog-A, and can be used for efficient simulations of various MTJ STOs. Moreover, an accurate phase noise generation approach, which ensures a reliable model, is proposed and successfully used in the Verilog-A model implementation. The model is experimentally validated by three different MTJ STOs under different bias conditions.CMOS circuits, which can enhance the limited output power of MTJ STOs to levels that are required in different applications, are proposed, implemented and tested. A novel balun-low noise amplifier (LNA), which can offer sufficient gain, bandwidth and linearity for MTJ STO-based magnetic field sensing applications, is proposed. Additionally, a wideband amplifier, which can be connected to an MTJ STO to form a highly-tunable microwave oscillator in a phase-locked loop (PLL), is also proposed. The measurement results demonstrate that the proposed circuits can be used to develop MTJ STO-based magnetic field sensing and microwave source applications.The investigation of possible STO-CMOS IC integration approaches demonstrates that the wire-bonding-based integration is the most suitable approach. Therefore, a giant magnetoresistance (GMR) STO is integrated with its dedicated CMOS IC, which provides the necessary functions, using the wire-bonding-based approach. The RF characterization of the integrated GMR STO-CMOS IC system under different magnetic fields and DC currents shows that such an integration can eliminate wave reflections. These findings open the possibility of using GMR STOs in magnetic field sensing and microwave source applications.
|
|
| 23. |
- Chen, Tingsu, et al.
(författare)
-
Wideband Amplifier Design for Magnetic Tunnel JunctionBased Spin Torque Oscillators
- 2012
-
Ingår i: Proc. of GigaHertz Symposium 2012.
-
Konferensbidrag (refereegranskat)abstract
- Spin torque oscillator (STO) is a novel current-control-oscillator (CCO), based on two spintronic effects: spin momentum transfer torque and magneto-resistance (MR). It features large tunability, miniature size, high integration level, high quality factor, high operation frequency, etc., which makes it a promising technology for microwave and radar applications. However, the STO is still an immature technology, which requires intensive research for improving the spectrum purity and the output power performance [1]. This paper proposes a wideband amplifier targeting magnetic tunnel junction (MTJ) type of STO device, which compensates the low output power of the STO. The MTJ STO devices can cover a large part of ultra-wideband (UWB) from 3 - 8 GHz and provide an output power from -60 dBm to -40 dBm by tuning the bias DC current and the magnetic field [2][3]. One important and potential application of STO device is a local oscillator (LO) in an RF transceiver. To achieve this task, the amplifier requires a gain of 45 - 65 dB. In addition, the source impedance of different MTJ STO devices varies from a dozen to several hundred Ohms, which makes the amplifier design challenging. An universal amplifier, which fulfills the extracted design requirements, is proposed. It is composed of two types of Balun-LNAs depending on the MR of STO devices as the input stages, a broadband limiting amplifier chain and an output buffer. A combination of a common source (CS) stage and a cross-coupled common gate (CG) stage is employed for the input Balun-LNA in the low impedance case while a cascoded CS stage is used in the high impedance case. The output of both LNAs is connected to a limiting amplifier chain, which provides enough voltage gain. An output buffer is used as the output stage to convert the balanced output to single-ended output and to match the output impedance to 50 Ohms. The proposed wideband amplifier for MTJ STO is implemented in a 65nm CMOS process with 1.2 V supply. In the band of interest, it exhibits 55 dB gain with a maximum noise figure (NF) of 4.5 dB in the small MR case, and a 59 dB gain with a maximum NF of 3 dB in the large MR case. Besides the low noise performance and the high gain, the simulation results of the proposed amplifier also show that it has low power consumption and moderate impedance matching in the frequency range of 3 - 8 GHz, which is suitable for MTJ STO applications.
|
|
| 24. |
- Fernandez-Anez, Nieves, et al.
(författare)
-
Current Wildland Fire Patterns and Challenges in Europe : A Synthesis of National Perspectives
- 2021
-
Ingår i: Air, Soil and Water Research. - : SAGE Publications. - 1178-6221. ; 14, s. 1-19
-
Forskningsöversikt (refereegranskat)abstract
- Changes in climate, land use, and land management impact the occurrence and severity of wildland fires in many parts of the world. This is particularly evident in Europe, where ongoing changes in land use have strongly modified fire patterns over the last decades. Although satellite data by the European Forest Fire Information System provide large-scale wildland fire statistics across European countries, there is still a crucial need to collect and summarize in-depth local analysis and understanding of the wildland fire condition and associated challenges across Europe. This article aims to provide a general overview of the current wildland fire patterns and challenges as perceived by national representatives, supplemented by national fire statistics (2009–2018) across Europe. For each of the 31 countries included, we present a perspective authored by scientists or practitioners from each respective country, representing a wide range of disciplines and cultural backgrounds. The authors were selected from members of the COST Action “Fire and the Earth System: Science & Society” funded by the European Commission with the aim to share knowledge and improve communication about wildland fire. Where relevant, a brief overview of key studies, particular wildland fire challenges a country is facing, and an overview of notable recent fire events are also presented. Key perceived challenges included (1) the lack of consistent and detailed records for wildland fire events, within and across countries, (2) an increase in wildland fires that pose a risk to properties and human life due to high population densities and sprawl into forested regions, and (3) the view that, irrespective of changes in management, climate change is likely to increase the frequency and impact of wildland fires in the coming decades. Addressing challenge (1) will not only be valuable in advancing national and pan-European wildland fire management strategies, but also in evaluating perceptions (2) and (3) against more robust quantitative evidence.
|
|
| 25. |
- Fernández Schrunder, Alejandro, 1993-, et al.
(författare)
-
A Bioimpedance Spectroscopy Interface for EIM Based on IF-Sampling and Pseudo 2-Path SC Bandpass ΔΣ ADC
- 2024
-
Ingår i: IEEE Transactions on Biomedical Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1932-4545 .- 1940-9990. ; , s. 1-13
-
Tidskriftsartikel (refereegranskat)abstract
- This paper presents a low-noise bioimpedance (bio-Z) spectroscopy interface for electrical impedance myography (EIM) over the 1 kHz to 2 MHz frequency range. The proposed interface employs a sinusoidal signal generator based on direct-digital-synthesis (DDS) to improve the accuracy of the bio-Z reading, and a quadrature low-intermediate frequency (IF) readout to achieve a good noise-to-power efficiency and the required data throughput to detect muscle contractions. The readout is able to measure baseline and time-varying bio-Z by employing robust and power-efficient low-gain IAs and sixth-order single-bit bandpass (BP) ΔΣ ADCs. The proposed bio-Z spectroscopy interface is implemented in a 180 nm CMOS process, consumes 344.3 - 479.3 μ W, and occupies 5.4 mm 2 area. Measurement results show 0.7 mΩ/√Hz sensitivity at 15.625 kHz, 105.8 dB SNR within 4 Hz bandwidth, and a 146.5 dB figure-of-merit. Additionally, recording of EIM in time and frequency domain during contractions of the bicep brachii muscle demonstrates the potential of the proposed bio-Z interface for wearable EIM systems.
|
|
