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1.	Lee, S. K., et al. (författare) Reduction of the Schottky barrier height on silicon carbide using Au nano-particles 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:9, s. 1433-1440 Tidskriftsartikel (refereegranskat)abstract By the incorporation of size-selected Au nano-particles in Ti Schottky contacts on silicon carbide, we could observe considerably lower the barrier height of the contacts. This result could be obtained for both n- and p-type Schottky contacts using current-voltage and capacitance voltage measurements. For n-type Schottky contacts, we observed reductions of 0.19-0.25 eV on 4H-SiC and 0.15-0.17 eV on 6H-SiC as compared with particle-free Ti Schottky contacts. For p-type SiC, the reduction was a little lower with 0.02-0.05 eV on 4H- and 0.10-0.13 eV on 6H-SiC. The reduction of the Schottky barrier height is explained using a model with enhanced electric field at the interface due to the small size of the circular patch and the large difference of the barrier height between Ti and Au.
2.	Linder, M., et al. (författare) On DC modeling of the base resistance in bipolar transistors 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:8, s. 1411-1418 Tidskriftsartikel (refereegranskat)abstract The total base resistance R-BTot constitutes a crucial parameter in modeling bipolar transistors. The significant physical effects determining R-BTot are current crowding and conductivity modulation in the base, both causing reduction of R-BTot With increasing base current I-B. In this paper, it is shown that the reduction of R-BTot(I-B) With increasing I-B is directly related to the physical effect dominating in the base. A new model for R-BTot(I-B) is presented where a parameter alpha is introduced to account for the contributions of current crowding and conductivity modulation in the base. Theoretically, alpha is equal to 0.5 when conductivity modulation is dominant and close to 1.0 when current crowding is the most significant effect. This was verified by measurements and simulations using a distributed transistor model which accounts for the lateral distribution of the base current and the stored base charge. The model proposed for R-BTot(I-B) is very suitable for compact transistor modeling since it is given in a closed form expression handling both current crowding and conductivity modulation in the base. An accurate extraction procedure of the model parameters is also presented.
3.	Danielson, E., et al. (författare) Investigation of thermal properties in fabricated 4H-SiC high power bipolar transistors 2003 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 47:4, s. 639-644 Tidskriftsartikel (refereegranskat)abstract Silicon carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximum current gain of approximately 10 times, and a breakdown voltage of 450 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 degreesC, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. The device was also tested in a switched setup, showing fast turn on and turn off at 1 MHz and 300 V supply voltage. Device simulations have been used to analyze the measured data. The thermal conductivity is fitted against the self-heating, and the lifetime in the base is fitted against the measurement of the current gain.
4.	Bertilsson, Kent, et al. (författare) The Effect of Different Transport Models in Simulation of High Frequency 4H-SiC and 6H-SiC Vertical MESFETs 2001 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 45:5, s. 645-653 Tidskriftsartikel (refereegranskat)abstract A full band Monte Carlo (MC) study of the high frequency performance of a 4H-SiC Short channel vertical MESFET is presented. The MC model used is based on data from a full potential band structure calculation using the local density approximation to the density functional theory. The MC results have been compared with simulations using state of the art drift-diffusion and hydrodynamic transport models. Transport parameters such as mobility, saturation velocity and energy relaxation time are extracted from MC simulations
5.	Danielsson, E., et al. (författare) The influence of band offsets on the IV characteristics for GaN/SiC heterojunctions 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:6, s. 827-835 Tidskriftsartikel (refereegranskat)abstract GaN/SiC heterojunctions can improve the performance considerably for bipolar transistors based on SiC technology. In order to fabricate such devices with a high current gain, the origin of the low turn-on voltage for the heterojunction has to be investigated, which is believed to decrease the minority carrier injection considerably. In this work heterojunction diodes are compared and characterized. For the investigated diodes, the GaN layers have been grown by molecular beam epitaxy (MBE), metal organic chemical vapor deposition, and hydride vapor phase epitaxy. A diode structure fabricated with MBE is presented here, whereas others are collected from previous publications. The layers were grown either with a low temperature buffer, AIN buffer, or without buffer layer. The extracted band offsets are compared and included in a model for a recombination process assisted by tunneling, which is proposed as explanation for the low turn-on voltage. This model was implemented in a device simulator and compared to the measured structures, with good agreement for the diodes with a GaN layer grown without buffer layer. In addition the band offset has been calculated from Schottky barrier measurements, resulting in a type II band alignment with a conduction band offset in the range 0.6-0.9 eV. This range agrees well with the values extracted from capacitance-voltage measurements.
6.	Domeij, Martin, et al. (författare) Dynamic avalanche in Si power diodes and impact ionization at the nn(+) junction 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:3, s. 477-485 Tidskriftsartikel (refereegranskat)abstract The reverse recovery failure limit was measured with an optical technique for power diodes which sustain high levels of dynamic avalanche. Measurements and simulations indicate that these diodes withstand dynamic avalanche at the pn-junction and eventually fail as a result of a strongly inhomogeneous current distribution caused by the onset of impact ionisation at the diode nn(+) junction - a mechanism similar to the reverse bias second breakdown of bipolar transistors.
7.	Grahn, J. V., et al. (författare) A low-complexity 62-GHz f(T) SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:3, s. 549-554 Tidskriftsartikel (refereegranskat)abstract A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900 degrees C for 10 s as the highest temperature step. A very high current gain of almost 2000 and cut off frequency of 62 GHz were achieved for a uniform 12% Ge profile. The breakdown voltage BVCEO and forward Early voltage were equal to 2.9 and 6.5 V, respectively.
8.	Heinle, Ulrich, et al. (författare) Modeling and characterization of capacitive coupling in trench-isolated structures on SOI substrates 2004 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 48:1, s. 43-49 Tidskriftsartikel (refereegranskat)
9.	Hellberg, Per-Erik, et al. (författare) Threshold voltage control for PMOSFETs using an undoped epitaxial Si channel and a p(+)-SixGe1-x gate 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:11, s. 2085-2088 Tidskriftsartikel (refereegranskat)abstract This paper examines experimentally the performance of PMOSFETs with an undoped epitaxial Si channel in combination with a p(+)-SixGe1-x gate electrode. The channel doping profiles were made using shallow As-implantation followed by selective epitaxy of undoped Si to different thicknesses of 40, 80 and 120 nm. The p(+)-SixGe1-x gate with different values of x was used to tailor the threshold voltage. The transconductance and saturation current were found to increase and the threshold voltage to decrease with increasing thickness of the undoped Si channel for the same gate material. Increasing Ge content in the p(+)-SixGe1-x gate resulted in an increased threshold voltage. Compared to the p(+)-Si gate, the threshold voltage was increased by 0.15 and 0.35 V with a p(+)-Si0.79Ge0.21 and p(+)-Si0.53Ge0.47 gate, respectively, independently of the Si channel thickness. Therefore, the use of a p(+)-SixGe1-x gate introduces an extra degree of freedom when designing the channel for high performance PMOSFETs.
10.	Jonsson, Rolf, et al. (författare) Computational load pull simulations of SiC microwave power transistors 2003 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 47:11, s. 1921-1926 Tidskriftsartikel (refereegranskat)abstract The design of power transistors for microwave applications requires a good understanding of their large signal behaviour in a real circuit context. The computational load-pull simulation technique is a powerful new way to evaluate the full time-domain voltages and currents of microwave power transistors during realistic operation. With this method it is possible to relate details in the time domain voltages and currents to corresponding variations in carrier densities, electrical field, etc. in the device. We have utilised the standard device simulator Medici, directly driven by sine voltage sources on both input and output. The resulting data from the simulations was then analysed using Matlab. Several 4H-SiC MESFET structures were evaluated by this technique and we found the p-type buffer layer doping and thickness to be crucial to obtain an optimum RF power. A 4H-SiC MESFET structure was found to have an output power of 6.2 W/mm at 1 GHz. ⌐ 2003 Elsevier Ltd. All rights reserved.
11.	Koo, S. M., et al. (författare) Electrical characteristics of metal-oxide-semiconductor capacitors on plasma etch-damaged silicon carbide 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:9, s. 1375-1380 Tidskriftsartikel (refereegranskat)abstract The characteristics of metal-oxide-semiconductor (MOS) capacitors formed on inductively coupled plasma (ICP) etch-damaged SiC have been investigated. MOS capacitors were prepared by dry-oxidation on ICP-etch-damaged n- and p-type. 6H- and 4H-SiC. The effect of a sacrificial oxidation treatment on the damaged surfaces has also been examined. Capacitance-voltage and current-voltage measurements of these capacitors were performed and referenced to those of simultaneously prepared control samples without etch damage. The effective interface densities (N-IT) and fixed oxide charges (Q(V)) of etch-damaged samples have been found to increase while the breakdown field strength (E-BD) of the oxide decreases. The barrier height (phib) at the SiC-SiO2, interface, determined from a Fowler-Nordheim analysis, decreased for MOS capacitors on etch-damaged surfaces. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged SiC.
12.	Lee, S. K., et al. (författare) Low resistivity ohmic titanium carbide contacts to n- and p-type 4H-silicon carbide 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:7, s. 1179-1186 Tidskriftsartikel (refereegranskat)abstract Low resistivity Ohmic contacts of epitaxial titanium carbide to highly doped n- (1.3 x 10(19) cm(-3)) and p- (>10(20) cm(-3)) type epilayer on 4H-SiC were investigated. The titanium carbide contacts were epitaxially grown using coevaporation with an e-beam for Ti and a Knudsen cell for C-60 in a UHV system. A comparison of epitaxial evaporated Ti Ohmic contacts on p(+) epilayer of 4H-SiC is also given. The as-deposited TiC Ohmic contacts showed a good Ohmic behavior and the lowest contact resistivity (rho(C)) was 7.4 x 10(-7) Ohm cm(2) at 200 degrees C for n-type, and 1.1 x 10(-4) Ohm cm(2) at 25 degrees C for p-type contacts. Annealing at 950 degrees C did not improve the Ohmic contact to n-type 4H-SiC, but instead resulted in an increase in rho(C) to 4.01 x 10(-5) Ohm cm(2) at 25 degrees C. In contrast to n-type, after annealing at 950 degrees C the specific rho(C) for p-type SiC reached its lowest value of 1.9 x 10(-5) Ohm cm(2) at 300 degrees C. Our results indicate that co-evaporated TiC contacts to n- and p-type epilayers of 4H-SiC should not require a higher post-annealing temperature, contrary to earlier works. Material characteristics, utilizing X-ray diffraction, Low energy electron diffraction, Rutherford backscattering spectrometry, transmission electron microscopy, and X-ray photoelectron spectroscopy measurements are also discussed.
13.	Ma, P. X., et al. (författare) An analytical model for space-charge region capacitance based on practical doping profiles under any bias conditions 2001 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 45:1, s. 159-167 Tidskriftsartikel (refereegranskat)abstract An analytical model is presented For quasi-static capacitance of the space-charge region in a p-n junction. The model is valid for realistic junction doping profiles under any bias conditions. It consists of local models in three bias regions. For the high-reverse bias region, a novel analytical model is derived. For the moderate-bias region, an empirical model commonly used in SPICE is adopted. Finally, for the high-forward bias region, the junction profiles are approximated by linearly-graded junctions. Existing analytical models are then modified appropriately to characterize both high-injection and heavy-doping effects for advanced bipolar transistors. Compared to previously developed analytical models or existing empirical models, as well as numerical simulation results, the analytical model presented here shows an improved accuracy and therefore provides a better tool For both device and circuit simulations.
14.	Malm, B. Gunnar, et al. (författare) Implanted collector profile optimization in a SiGeHBT process 2001 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 45:3, s. 399-404 Tidskriftsartikel (refereegranskat)abstract Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f(T) to be increased without degrading the collector emitter breakdown voltage BVCEO. The fabricated devices demonstrate a highest f(T) of 60 GHz. Depending on the collector profile BVCEO values between 1.5 and 2 V were obtained.
15.	Malm, B. Gunnar, et al. (författare) Influence of transient enhanced diffusion of the intrinsic base dopant profile on SiGeHBT DC and HF characteristics 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:10, s. 1747-1752 Tidskriftsartikel (refereegranskat)abstract The influence of transient enhanced boron out-diffusion from the intrinsic base, caused by excess silicon interstitials created during the extrinsic base implantation, has been investigated for a non-selective SiGe HBT process. Devices with different designs of the extrinsic base region were fabricated, where some designs allowed part of the epitaxial base to be implanted with a high boron dose, hereby increasing the number of silicon interstitials close to the intrinsic device. These devices showed a marked degradation of DC characteristics and HF performance. 2D-device simulations were used to investigate the sensitivity in DC and HF parameters to vertical base profile changes. Good agreement was obtained between measured and simulated DC and HF characteristics.
16.	Malm, B. Gunnar, et al. (författare) Mixed mode circuit and device simulation of RF harmonic distortion for high-speed SiGeHBTs 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:10, s. 1567-1571 Tidskriftsartikel (refereegranskat)abstract Mixed mode circuit and device simulation has been used to investigate the linearity properties-harmonic distortion of high-speed low voltage SiGe heterojunction bipolar transistors (HBTs). The simulation test-circuit included the active device, modeled by finite element simulation, as well as passive elements in a SPICE circuit for DC-feed and AC-coupling of the RF-signal. Different Ge-profiles for reduced harmonic distortion have been investigated and compared to a conventional high-speed graded Ge-profile. To find an optimized Ge-profile for RF-applications other figure-of-merits, such as maximum cut-off frequency and minimum noise figure were also simulated. Using the same mixed mode simulation approach the design of the epitaxial collector doping profile for high breakdown voltage, high cut-off frequency and reduced harmonic distortion was investigated.
17.	Nawaz, M, et al. (författare) A theoretical optimization of GaInP/GaInAs/GaAs based 980 nm Al-free pump laser using self-consistent numerical simulation 2003 Ingår i: Solid-State Electronics. - : Elsevier Science B.V., Amsterdam.. - 0038-1101 .- 1879-2405. ; 47:2, s. 291-295 Tidskriftsartikel (refereegranskat)abstract Using self-consistent two-dimensional numerical simulation (LASTIP), the layer structure of the laser diodes is optimized. A ridge waveguide structure with GaInAs/GaAs and GaInAs/GaInAsP active regions has been simulated. The influence of the well numbers and waveguide thicknesses on the threshold current is studied. Compared to GaInAs/ GaAs, GaInAs/GaInAsP active region suffers from larger spread in the threshold current due to non-uniformities in the carrier density with increasing quantum wells. Simulations have been performed for different temperatures and at different cavity lengths.
18.	Nilsson, Hans-Erik, et al. (författare) An Investigation of the blocking characteristics of the Permeable Base Transistor 1998 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 42:3, s. 297-305 Tidskriftsartikel (refereegranskat)abstract A numerical study of the blocking characteristics of the Permeable Base Transistor (PBT) is presented. The PBT is regarded as a promising transistor structure for high voltage and high frequency applications. Numerical studies of the PBT were focused on the high frequency figure of merits or the breakdown characteristics of the Schottky gate. A device designed for high frequency and high voltage switching should be optimized for large blocking and fast switching. The trade off between blocking and speed is a complicated matter which depends strongly on the geometry and doping level. In this work we studied the blocking characteristics for a Silicon PBT with regard to the doping level and doping profile, gate thickness and gate to drain distance. A scaling formalism was developed in order to estimate the transistor performance for a wide range of doping levels and geometrical combinations. A design example is presented of a normally off transistor that can block a drain to source voltage of 10 V while the unity current gain frequency fT value for Vgs = 0.2 V is higher than 7 GHz.
19.	Olsson, Jörgen, et al. (författare) Investigation of the Current-Voltage Behavior of a Combined Schottky-p-n diode 1992 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 35:9, s. 1229-1231 Tidskriftsartikel (refereegranskat)
20.	Persson, Clas, et al. (författare) Plasma-induced band edge shifts in 3C-, 2H-, 4H-, 6H-SiC and Si 2000 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 44:3, s. 471-476 Tidskriftsartikel (refereegranskat)abstract Plasma-induced energy shifts of the conduction band minimum and of the valence band maximum have been calculated for 3C-, 2H-, 4H-, 6H-, 6H-SiC and Si. The resulting narrowing of the fundamental band gap and of the optical band gap are presented. The method utilized is based on a zero-temperature formalism within the random phase approximation. Electron-electron, hole-hole, electron-hole, electron-optical phonon and hole-optical phonon interactions have been taken into account. The calculations are based on band structure data from a relativistic, full-potential band structure calculation.
21.	Persson, S, et al. (författare) A charge sheet model for MOSFETs with an abrupt retrograde channel - Part I. Drain current and body charge 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:12, s. 2209-2216 Tidskriftsartikel (refereegranskat)abstract Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, psi(s), by the potential at the interface between the intrinsic surface layer and the doped substrate, psi(xi).
22.	Persson, S, et al. (författare) A charge sheet model for MOSFETs with an abrupt retrograde channel - Part II. Charges and intrinsic capacitances 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:12, s. 2217-2225 Tidskriftsartikel (refereegranskat)abstract The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.
23.	Vestling, Lars, et al. (författare) Drift Region Optimization of Lateral RESURF Devices 2002 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 46:8, s. 1177-1184 Tidskriftsartikel (refereegranskat)
24.	Zetterling, Carl-Mikael, et al. (författare) A novel UMOS capacitor test structure for SiC devices 1996 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 39:9, s. 1396-1397 Tidskriftsartikel (refereegranskat)abstract In this paper we propose the use of U-grooved MOS capacitors to investigate oxides intended for U-grooved MOSFETs and IGBTs in silicon carbide. The UMOS capacitor uses only two mask layers, and has vertically etched walls and a gate contact that overlaps the step. We have manufactured UMOS capacitors in n-type 6H SiC with dry thermal gate oxides, and compared the capacitance voltage characteristics to those of flat reference capacitors. It was found that the general appearance of capacitance-voltage curves was unchanged by the addition of the vertical grooves, although the leakage through the oxide was increased. The oxide thickness on the sidewalls was approximately the same as on the flat parts of the devices. Copyright Â© 1996 Elsevier Science Ltd.
25.	Adnane, Bouchaib, et al. (författare) Photoluminescence study of nanocrystalline-Si(Ge) embedded in mesoporous silica 2009 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 53:8, s. 862-864 Tidskriftsartikel (refereegranskat)abstract Photoluminescence (PL) properties of mesoporous silica (MS) samples incorporated with Si or Ge nanocrystals (nc) have been investigated with various excitation powers and post-RTA processes. The analysis of experimental results revealed a superlinear intensity dependence (m = 1.7) in the MS reference sample without nanocrystals, while a sublinear behavior (m = 0.8) is observed for the nc-Si in MS. It thus suggests the same recombination responsible for the luminescence at similar to 2.75 eV for both samples, but different kinetic limitations for the carrier transfer processes. Si nanocrystals play in this case an important role in generating more photo-excited carriers, enhancing the PL intensity.
26.	Alshebly, Wisam, et al. (författare) Transcapacitances Modeling in ultra-thin gate-all-around junctionless nanowire FETs, including 2D quantum confinement 2023 Ingår i: Solid-State Electronics. - : PERGAMON-ELSEVIER SCIENCE LTD. - 0038-1101 .- 1879-2405. ; 200 Tidskriftsartikel (refereegranskat)abstract In this work, we propose an analytical model for the intrinsic transcapacitances in ultra-thin gate-all-around junctionless nanowire field effect transistors in the presence of confined energy states of electrons. The validity of the developed model is confirmed from deep depletion to accumulation and from linear to saturation, based on the numerical solution of the Schrodinger equation using Technology Computer Aided Design (TCAD) simulations. This represents an important stage toward AC small signal analysis of junctionless nanowire-based circuits.
27.	Andersson, J. Y., et al. (författare) SiGe/Si quantum structures as a thermistor material for low cost IR microbolometer focal plane arrays 2011 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 60:1, s. 100-104 Tidskriftsartikel (refereegranskat)abstract Uncooled microbolometer thermal infrared detector technology is presently revolutionizing the infrared technology field. Essential improvement of the cost/performance ratio would be achieved by microbolometer arrays with higher sensitivity, since this allows the use of simpler and less costly camera optics, which implies a lower cost of the complete IR camera. The sensitivity of the microbolometers depends critically on the signal-to-noise ratio of the integrated thermistor material, which is set by its temperature coefficient of resistance (TCR) and noise characteristics. In this work we have investigated the use of epitaxial silicon-germanium/silicon (SiGe/Si) quantum well (QW) structures as a thermistor material. Si0.68Ge0.32/Si QW structures typically give a TCR of 3.0%/K and low noise values. A calculation of the noise equivalent temperature NETD of a bolometer gives 25 mK using the following assumptions: f-number = 1, 30 Hz video frame rate for a 640 x 480 array, with a pixel size 25 x 25 mu m. Higher TCR values are foreseen for SiGe/Si quantum dot structures, and the noise is expected to be similar to the QW based structures.
28.	Ankarcrona, Johan, et al. (författare) Simulation and modeling of the substrate contribution to the output resistance for RF-LDMOS power transistors 2004 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:5, s. 789-797 Tidskriftsartikel (refereegranskat)abstract High frequency substrate losses for RF MOSFETs are analyzed using numerical device simulation. The results show that losses in devices made on low resistivity substrate occur through the substrate while losses in devices made on high resistivity substrate in the high frequency region occur along the surface through the device (source–drain). An equivalent circuit model is developed which accurately describes the off-state losses. Based on the model significant improvements in terms of output resistance are demonstrated, using an improved device on high resistivity substrate.
29.	Ayala, Christopher L., et al. (författare) Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts 2015 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 113, s. 157-166 Tidskriftsartikel (refereegranskat)abstract Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.
30.	Azam, Sher, et al. (författare) Pulse Input Class-C Power Amplifier Response of SiC MESFET using Physical Transistor Structure in TCAD 2008 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:5, s. 740-744 Tidskriftsartikel (refereegranskat)abstract The switching behavior of a previously fabricated and tested SiC transistor is studied in Class-C amplifier in TCAD simulation. The transistor is simulated for pulse input signals in Class-C power amplifier. The simulated gain (dB), power density (W/mm) and power added efficiency (PAE%) at 500 MHz, 1, 2 and 3 GHz was studied using computational TCAD load pull simulation technique. A Maximum PAE of 77.8% at 500 MHz with 45.4 dB power gain and power density of 2.43 W/mm is achieved. This technique allows the prediction of switching response of the device for switching amplifier Classes (Class-C–F) before undertaking an expensive and time consuming device fabrication. The beauty of this technique is that, we need no matching and other lumped element networks for studying the large signal behavior of RF and microwave transistors.
31.	Bengtsson, Olof, et al. (författare) A Computational Load-Pull Method with Harmonic Loading for High-Efficiency Investigations 2009 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 53:1, s. 86-94 Tidskriftsartikel (refereegranskat)abstract In this paper a method for TCAD evaluation of RF-power transistors in high-efficiency operation using harmonic loading is presented. The method is based on large signal time-domain computational load-pull. Active loads are used in the harmonic load-pull for simulation time reduction. With the method device performance under different harmonic load impedance can be investigated at an early stage in the design process. Alternative designs can be compared and the mechanisms affecting device efficiency in class-F can be studied at chip-level. For method validation, a case study is made on an LDMOS transistor. The transistor is load-pulled in class-AB and then optimized for efficiency at 2f0 and 3f0 using a novel approach with passive fundamental load and active harmonic loads. A swept simulation is conducted using passive fundamental and harmonic loads. Waveforms in compression are analyzed and the mechanisms creating the increased efficiency in class-F are identified by a comparative study to class-AB. Class-F harmonic termination is shown to give a 17% overall reduction of dissipated power and a 9% increase in output power. The expected efficiency increase is about 3–10% in the compression region depending on level of compression.
32.	Bengtsson, Olof, et al. (författare) Investigation of the non-linear input capacitance in LDMOS transistors and its contribution to IMD and phase distortion 2008 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:7, s. 1024-1031 Tidskriftsartikel (refereegranskat)abstract In this paper the mechanisms causing the capacitive, reactive non-linearities in a lateral double diffused MOS, LDMOS, transistor are investigated. The non-linear input capacitance under load-line power match is extracted and analyzed. Computational TCAD load-pull is used to analyze the effect of non-linear capacitance on two-tone intermodulation distortion and AM–PM conversion in class-A operation. High-frequency measurements have been made to verify the use of 2D numerical device simulations for the analysis. It is found that the input capacitance, Cgg, of the LDMOS transistor working under power match conditions is a strongly non-linear function of gate voltage Vg but with an almost linear initial increase in Cgg. The voltage dependence of Cgg is found to mainly affect higher order IMD products in class-A operation. Transient simulations however show that Cgg seriously contributes to the onset of AM–PM conversion well below the 1 dB compression point.
33.	Bertilsson, Kent, et al. (författare) Calculation of lattice heating in SiC RF power devices 2004 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:12, s. 1721-1725 Tidskriftsartikel (refereegranskat)abstract Silicon carbide MESFET devices are suitable for high-speed and high-power applications. In this paper we are studying thermal effects in 4H-SiC RF power devices. The simulations are based on a combination of 2D device simulations for the electrical transport, and 3D thermal simulations for the lattice heating. We show that the method gives good accuracy, efficiency, flexibility and capacity dealing with tasks, where a 2D coupled electrical-thermal simulation is not sufficient. We also present an improvement of Roschke and Schwierz mobility model, based on Monte Carlo simulations for the temperature dependencies of the mobility parameters beta and v(sat).
34.	Bertilsson, Kent, et al. (författare) The power of using automatic device optimization, based on iterative device simulation, in design of high-performance devices 2004 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:10-11, s. 1721-1725 Tidskriftsartikel (refereegranskat)abstract An automatic optimization tool for semiconductor devices based on iterative device simulations is developed. The tool is used for optimization of different kinds of semiconductor devices using various performance measures. High performance optimization algorithms, both local and global, are used to achieve an efficient design in shortest possible time. In this paper the effects of different optimization algorithms, performance measures, and number of variables in the optimization are studied. Both the computational efficiency and the devices achieved with different performance measures are studied. We give a demonstration of the usefulness of this method in a comparison between different device topologies, which have been optimized for best performance.
35.	Bleichner, H, et al. (författare) A study of turn-off limitations and failur mechanisms in GTO thyristors by means of 2-D time-resolved optical measurements 1992 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 35:11, s. 1683-1695 Tidskriftsartikel (refereegranskat)
36.	Bleichner, H, et al. (författare) Flying-spot scanning for the separate mapping of resistivity and minority-cariier lifetime in silicon 1986 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 29:8, s. 779-786 Tidskriftsartikel (refereegranskat)
37.	Bohlin, K, et al. (författare) A p-channel MESFET on silicon using erbium gate 1985 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 28:9, s. 15- Tidskriftsartikel (refereegranskat)
38.	Chen, Tingsu, et al. (författare) Integration of GMR-based spin torque oscillators and CMOS circuitry 2015 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 111, s. 91-99 Tidskriftsartikel (refereegranskat)abstract This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm(2). The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies. (C) 2015 Elsevier Ltd. All rights reserved.
39.	Ciechonski, Rafal, 1976-, et al. (författare) Evaluation of MOS structures processed on 4H–SiC layers grown by PVT epitaxy 2005 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 49:12, s. 1917-1920 Tidskriftsartikel (refereegranskat)abstract MOS capacitors have been fabricated on 4H–SiC epilayers grown by physical vapor transport (PVT) epitaxy. The properties were compared with those on similar structures based on chemical vapor deposition (CVD) layers. Capacitance–voltage (C–V) and conductance measurements (G–V) were performed in the frequency range of 1 kHz to 1 MHz and also at temperatures up to 475 K. Detailed investigations of the PVT structures indicate a stable behaviour of the interface traps from room temperature up to 475 K. The amount of positive oxide charge QO is 6.83 × 109 cm−2 at room temperature and decreases with temperature increase. This suggests that the processed devices are temperature stable. The density of interface states Dit obtained by Nicollian–Brews conductance method is lower in the structure based on the PVT grown sample.
40.	de Sousa Pires, Jorge, et al. (författare) A new approach to the determination of MS-barrier heights from photoelectric data and/or an alternative way to determine the value of the Richardson constant 1982 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 25, s. 989- Tidskriftsartikel (refereegranskat)
41.	de Sousa Pires, Jorge, et al. (författare) A self consistent approach to Fowler plots 1984 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 27, s. 1029-1032 Tidskriftsartikel (refereegranskat)
42.	Dentoni Litta, Eugenio, et al. (författare) Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology 2014 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 98, s. 20-25 Tidskriftsartikel (refereegranskat)abstract This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.
43.	Dentoni Litta, Eugenio, et al. (författare) Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs 2015 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 108, s. 24-29 Tidskriftsartikel (refereegranskat)abstract High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.
44.	Donoval, D, et al. (författare) A self consistent approach of IV measurements on rectifying metal-semiconductor contacts 1989 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 32:11, s. 961-964 Tidskriftsartikel (refereegranskat)
45.	Driussi, F., et al. (författare) On the electron mobility enhancement in biaxially strained Si MOSFETs 2008 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:4, s. 498-505 Tidskriftsartikel (refereegranskat)abstract This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.
46.	Echtermeyer, T., et al. (författare) Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes 2007 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621 Tidskriftsartikel (refereegranskat)abstract Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
47.	Elfsten, B, et al. (författare) CALCULATIONS OF CHARGE DISTRIBUTIONS AND MINORITY-CARRIER INJECTION RATIO FOR HIGH-BARRIER SCHOTTKY DIODES 1985 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 28:7, s. 721-727 Tidskriftsartikel (refereegranskat)
48.	Elfsten, B, et al. (författare) Influence of metal sheet resistivity on the IV-characteristics of metal-semiconductor diodes 1984 Ingår i: Solid-State Electronics. - 0038-1101 .- 1879-2405. ; 27:4, s. 317- Tidskriftsartikel (refereegranskat)
49.	Engstrom, O., et al. (författare) Navigation aids in the search for future high-k dielectrics : Physical and electrical trends 2007 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 622-626 Tidskriftsartikel (refereegranskat)abstract From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.
50.	Farkas, Balazs, et al. (författare) Flexible Thin-Flm Transistors on Planarized Parylene Substrate with Recessed Individual Backgates 2014 Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 94, s. 11-14 Tidskriftsartikel (refereegranskat)abstract With novel design and fabrication techniques, InGaZnO-based thin-film transistors with individual recessed back-gates were fabricated on flexible and transparent polymer substrates. The key components for the fabrication include using a machine park optimized for Si process technology, low-adhesion, room temperature parylene coating, AlOx–ZnOx(Al)-based inorganic lift-off process, and a recessed individual gate concept. Transistors were built to validate the viability of the design as well as aforementioned techniques. The demonstrated approach could open up new design possibilities for cheap, flexible devices, while the recessed-gate concept shows promise towards the use of more brittle layers in our flexible thin-film electronic devices.

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