| 1. |
- Andersson, Ola, 1976-, et al.
(författare)
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Spectral shaping of DAC nonlinearity errors through modulation of expected errors
- 2001
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Ingår i: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on. - : IEEE. - 0780366859 ; , s. 417-420
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Konferensbidrag (refereegranskat)abstract
- Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included
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| 2. |
- Andreani, Pietro
(författare)
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A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor
- 2001
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Ingår i: The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001.. - 0780366859 ; 4, s. 714-717
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Konferensbidrag (refereegranskat)abstract
- A 1.8-GHz CMOS VCO is presented, employing a monolithic transformer as an inductance with voltage-controlled value. The design was implemented in a standard digital 0.6 μm, 2-metal CMOS process and exhibits a 10% tuning range with a 2.7 V supply voltage and a 9 mA supply current. Phase noise measurements show a worst-case phase noise of about -112 dBc/Hz at 3 MHz offset from the carrier
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| 3. |
- Bengtson, Håkan, 1971-, et al.
(författare)
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3V CMOS 0.35 u transimpedance receiver for optical applications
- 2001
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Ingår i: The 2001 IEEE International Symposium on Circuits and Systems, 2001. - Piscataway : IEEE. - 0780366859 ; , s. 69-71
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Konferensbidrag (refereegranskat)abstract
- A new class of receivers for optical applications is described. The novelty of the design is the high speed stage. The receiver is designed for low noise, high bandwidth and high transimpedance-bandwidth product. The receiver is driving a 50 Ω load. Post simulations on chip with all capacitance parasitics and a 0.5 pF diode capacitance, gives a 1.3 GHz bandwidth. For an input diode current of 1 uA=zero and 10 uA=one, the output signal is 0.15 V peak to peak and the output SNR is 23 dB
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| 4. |
- Eckerbert, Daniel, 1973-, et al.
(författare)
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Cycle-true leakage current modeling for CMOS gates.
- 2001
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Ingår i: IEEE International Symposium on Circuits and Systems ISCAS,2001. - Piscataway : IEEE. - 0780366859 ; , s. 507-510
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Konferensbidrag (refereegranskat)abstract
- This paper addresses cycle-true leakage current modeling for static CMOS gates. An approach to leakage power estimation is suggested which deals with some of the issues associated with the complex dynamic behavior of the gate. The paper discusses problems with defining gate leakage power. It then suggests a modeling approach, which separates the static leakage from the dynamic switch and short-circuit power. The model is used to achieve cycle-true leakage power estimation which is important as 20% of the power consumption in the designs of today can be leakage power. The importance of leakage power modeling will continue to grow as leakage power scales exponentially with reduced VT
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| 5. |
- Eriksson, Henrik, 1974-, et al.
(författare)
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A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.
- 2001
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Ingår i: IEEE International Symposium on Circuits and Systems ISCAS.,2001. - Piscataway : IEEE. - 0780366859 ; , s. 84-87
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Konferensbidrag (refereegranskat)abstract
- A fast and area-efficient 32-b Manchester carry-bypass adder with low energy-delay product is presented in this paper. The high speed is achieved by the use of optimized bypass circuitry and fast repeater elements in the carry path. The fabricated adder has a measured worst-case delay of 2.8 ns and consumes 30 μW/MHz
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| 6. |
- Eriksson, Henrik, 1974-, et al.
(författare)
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A regular parallel multiplier which utilizes multiple carry-propagate adders.
- 2001
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Ingår i: IEEE International Symposium on Circuits and Systems ISCAS.,2001. - Piscataway : IEEE. - 0780366859 ; , s. 166-169
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Konferensbidrag (refereegranskat)abstract
- A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers
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| 7. |
- Folkesson, Kalle, 1974-, et al.
(författare)
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Modeling of dynamic errors in algorithmic A/D converters
- 2001
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Ingår i: The 2001 IEEE International Symposium on Circuits and Systems, 2001. ISCAS 2001.. - Piscataway : IEEE. - 0780366859 ; , s. 455-458
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Konferensbidrag (refereegranskat)abstract
- In communication applications, the requirements on A/D converters are high and increasing. To be able to design high-perfomance converters, it is important to understand the speed limitations. In this work, performance decrease caused by dynamic errors related to settling time of the switched circuits at high sampling frequencies is investigated
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| 8. |
- Magesacher, Thomas, et al.
(författare)
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An adaptive mixed-signal narrowband interference canceller for wireline transmission systems
- 2001
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Ingår i: The 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001.. - 0780366859 ; , s. 450-453
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Konferensbidrag (refereegranskat)abstract
- Narrowband radio transmitters like radio amateurs and broadcast radio stations are considered to be a serious problem for high-bitrate data transmission over twisted pairs. Due to its high power level, radio frequency interference (RFI) has the potential of overloading the receiver's analog-to-digital converter (ADC). Once the ADC is in saturation, any countermeasure taken in the digital domain will fail, so the problem has to be faced at least partly in the analog domain. This paper proposes an adaptive, mixed-signal, narrowband interference canceller employing a modified recursive least-squares (RLS) algorithm which is split into an analog and a digital part. The mixed-signal approach enables the circuit to generate an interference-cancelling signal of several MHz while operating the adaptive algorithm at some kHz. The structure is fast enough to prevent the ADC from overloading due to radio amateur interference, thus protecting the data transmission from interruption. Simulation results as well as measurements indicate a practical disturbance rejection potential of about 40-50 dB
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| 9. |
- Meißner, Michael, et al.
(författare)
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Accelerating volume rendering using an on-chip sram occupancy map
- 2001
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Ingår i: ISCAS 2001. - Piscataway, NJ : IEEE Communications Society. - 0780366859 ; , s. 757-760
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Konferensbidrag (refereegranskat)abstract
- One of the most severe problems for ray casting architectures is the waste of computation cycles and I/O bandwidth, due to redundant sampling of empty space. While several techniques exist for software implementations to skip these empty regions, few are suitable for hardware implementation. The few which have been presented either require a tremendous amount of logic or are not feasible for high frequency designs (i.e. running at 100 MHz) where latency is the one of the biggest issues. In this paper, we present an efficient space leaping approach which requires only a small amount of SRAM (4 Kbit for a 256 3 volume) and can be easily integrated into ray casting architectures. For each subcube of the volume, a bit is stored in an occupancy map, indicating whether the subcube is empty or not. Using a set of real-world datasets, we show that frame-rates well above 15 frames per second can be accomplished for the VIZARD II volume rendering architecture
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| 10. |
- Olsson, Thomas, et al.
(författare)
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Dual Supply-Voltage Scaling for Reconfigurable SoCs
- 2001
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Ingår i: The 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001.. - 0780366859 ; 2, s. 61-64
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Konferensbidrag (refereegranskat)abstract
- By partitioning a hardware design into several blocks and adjusting the voltage of the different blocks individually, an overall power consumption reduction is possible. An algorithm and a hardware solution for assigning two supply voltages to a design divided into blocks is presented. The two supply voltages are optimized using an on-chip controller. The on-chip controller assigns one of the two supply voltages to each block. This defines a solution suitable for reconfigurable designs
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| 11. |
- Piper, Johan, et al.
(författare)
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Realization of a floating-point A/D converter
- 2001
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Ingår i: Proceedings of 2001 IEEE International Symposium on Circuits and Systems. - 0780366859 ; 1, s. 404-407
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Konferensbidrag (refereegranskat)abstract
- A floating-point analog-to-digital converter (FP-ADC) with a linear architecture has been implemented using an amplifier network in front of a pipeline ADC. The amplifier network has outputs with binary weighted gains, each sampled separately. The signal with the proper gain is then converted in the ADC. This structure allows instant floating point exponent determination. The mismatches in the amplifier network has been analyzed and successfully reduced. A prototype FP-ADC is currently being manufactured in a 0.35 μm double-poly CMOS process. Post-layout simulations show an operating frequency in excess of 30 MS/s with 74 dB dynamic range and 8 bit resolution.
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| 12. |
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| 13. |
- Vesterbacka, Mark, 1966-, et al.
(författare)
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Design of encoders for linear-coded D/A converters
- 2000
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Ingår i: Proc. 2001 IEEE Int. Symp. on Circuits and Systems, ISCAS'01. - : IEEE. - 0780366859 ; , s. 524-527 vol.1
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Konferensbidrag (refereegranskat)abstract
- A linear increase of the source weights in a flash D/A converter has earlier been suggested to reduce the level of glitches associated with the code transitions. However, a limitation with this approach was that a straightforward conversion from an offset-binary number to a linear-coded number required a large amount of hardware. In this work, we present a new method that yields a more hardware efficient encoder. We also compare the proposed encoder with other encoders in terms of design complexity and glitch performance.
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| 14. |
- Yijun, Zhou, et al.
(författare)
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An 8-Bit, 100-MHz low glitch interpolation DAC
- 2001
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Ingår i: Proceedings of the 2001 IEEE International Symposium on Circuits and Systems. - 0780366859 ; 4, s. 116-119
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Konferensbidrag (refereegranskat)abstract
- This paper describes an 8-Bit, 100-MHz current steering CMOS low glitch interpolation digital to analog converter (DAC). It includes a 16-tap voltage controlled delay line and 8-Bit based linear interpolators, making the effective clock rate up to 1.6-GHz. With the linear interpolation, the requirement on the analog reconstruction filter is relaxed, and low glitch digital to analog conversion is achieved. The chip is fabricated with a 3.3 V, 0.35 μm digital CMOS process
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