| 1. |
- Andersson, Ola, 1976-, et al.
(författare)
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Dynamic element matching in decomposed digital-to-analog converters
- 2004
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Ingår i: Proc. IEEE NORCHIP'04. - Denmark : TechnoData A/S. - 0780385101 ; , s. 187-190
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Konferensbidrag (refereegranskat)abstract
- A dynamic element matching (DEM) technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed converter architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90% yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.
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| 2. |
- Andersson, Stefan, et al.
(författare)
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Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies
- 2004
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Ingår i: Proceedings of the Norchip 2004 Conference, Oslo, Norway, November. - 0780385101 ; , s. 123-126
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Konferensbidrag (refereegranskat)abstract
- In this paper, measurements of drain thermal noise for three NMOS devices with different channel lengths was carried out. The three NMOS devices were all implemented in a 0.18 μm CMOS technology, with channel lengths 0.18. 0.36, and 0.72 μm, respectively. The result was then compared with simulated data using the BSIM3- model and parameters provided by the vendor Large discrepancies between measurements and simulations were observed. This work was done in order to understand how to utilize transistor length as a design parameter to achieve optimal noise gures for wideband LNAs in deep submicron technologies.
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| 3. |
- Andrijevic, Goran, et al.
(författare)
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Multistandard receiver for home networking and digital media
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - NEW YORK : IEEE. - 0780385101 ; , s. 131-134
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Konferensbidrag (refereegranskat)abstract
- We propose a fully integrated multistandard receiver architecture that fulfills coming media and networking needs of homes. The receiver uses a dual-IF architecture to cover receive bands from 170 MHz to 920 MHz and the Industrial, Scientific and Medical (ISM) band at 2.4GHz. Key performance values meet the DVB-T, Zigbee, Bluetooth and 802.11b requirements (Sensitivity -72.5dBm. available SNR=28dB. Noise Figure 6.7dB. Adjacent Channel Protection Ratio-ACPR=-44dB, IIP3 = -11 dBm).
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| 4. |
- Aspemyr, Lars, et al.
(författare)
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A 0.6 V l .6 mW fully integrated voltage-controlled oscillator in 90 nm CMOS aiming for the GPS LI band
- 2004
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Ingår i: Proceedings - Norchip. - 0780385101 ; , s. 48-50
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Konferensbidrag (refereegranskat)abstract
- A fully integrated 0.6 V 2.6 mA VCO aimed for the GPS L1 band is realized in a 90 nm CMOS process. The VCO operates at 6.3 GHz and a divide-by-four circuit buffer provide the wanted 1575.42 MHz signal. The VCO has a measured phase noise of-103 dBc/Hz at 100kHz offset and a chip area of 1.15mm 2, including bondpads.
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| 5. |
- Cao, Cao, et al.
(författare)
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A Tool for Low-Power Synthesis of FSMs with Mixed Synchronous/Asynchronous State Memory
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - : IEEE. - 0780385101 ; , s. 199-202
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Konferensbidrag (refereegranskat)abstract
- An efficient way to obtain Finite-State Machines (FSMs) with low power consumption is to,partition the machine into two or more sub-FSMs and use dynamic power management, where all sub-FSMs not active are shut down, to reduce dynamic power dissipation. In this paper we focus on FSM partitioning algorithms and RT-level power estimation functions that are the key issues in the design of a CAD tool for synthesis of low-power partitioned FSMS. We target an implementation architecture that is based on both synchronous and asynchronous state memory elements that enables larger power reductions than fully synchronous architectures do. Power reductions of up to 77% have been achieved at a cost of an increase in area of 18%.
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| 6. |
- Duo, Xinzhong, et al.
(författare)
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A DC-13GHz LNA for UWB RFID applications
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - 0780385101 ; , s. 241-244
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Konferensbidrag (refereegranskat)abstract
- In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.
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| 7. |
- Hitana, Tahar, et al.
(författare)
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Bridging concurrent and non-concurrent error detection in FIR filters
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - NEW YORK : IEEE. - 0780385101 ; , s. 75-78
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Konferensbidrag (refereegranskat)abstract
- Maintaining high reliability in fault detection is a prominent concern in case of life critical missions. In this paper, we describe how the invariant-based technique has been improved and extended. It is shown that the detection time latency can be considerably reduced. In order to widen the fault coverage and fully control the detection time, a cost effective nonconcurrent error detection scheme is proposed. The results indicate that, for any specified checking period, 100% non-concurrent error detection is possible.
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| 8. |
- Jervan, Gert, 1974-, et al.
(författare)
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An Improved Estimation Methodology for Hybrid BIST Cost Calculation
- 2004
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Ingår i: IEEE Norchip 2004,2004. - 0780385101 ; , s. 297-300
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Konferensbidrag (refereegranskat)abstract
- This paper presents an improved estimation methodology for hybrid BIST cost calculation. In a hybrid BIST approach the test set is assembled from pseudorandom and deterministic test patterns. The efficiency of the hybrid BIST approach is largely determined by the ratio of those test patterns in the final test set. Unfortunately exact algorithms for finding the test sets are computationally very expensive. Therefore in this paper we propose an improved estimation methodology for fast calculation of the hybrid test set. The methodology is based on real fault simulation results and experimental results have shown that the method is more accurate than the statistical method proposed earlier.
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| 9. |
- Jonsson, Fredrik
(författare)
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A Single Chip 802.11 a/b/g WLAN Transceiver
- 2004
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Ingår i: 22nd Norchip Conference. - 0780385101 ; , s. 233-236
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Konferensbidrag (refereegranskat)abstract
- A dual-band triple mode radio compliant with the IEEE 802.11 a/b/g standard implemented in a 0.18 μm CMOS process is presented. The transceiver is compatible with a large number of basebands due to its flexible interface towards AD / DA converters and on-chip automatic calibration of on-chip filters and oscillators. The transceiver achieves a receiver noise figure of 4.9/5.6dB for the 2.4GHz/5GHz bands, respectively, and a minimum transmit error vector magnitude (EVM) of 2.5% for both bands. A quadrature accuracy of 0.3° in phase and 0.05dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a better than -34dBc total integrated phase noise. The chip passes ±2kV human body model ESD testing on all pins, including the RF pins. The total die area is 12mm2. The power consumption is 207mW in the receive mode and 247mW in the transmit mode using a 1.8V supply.
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| 10. |
- Kozmin, Kirill, et al.
(författare)
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A low power, propagation delay stable, continuous-time comparator
- 2004
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Ingår i: Proceedings. - Piscataway, NJ : IEEE Communications Society. - 0780385101 ; , s. 261-264
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Konferensbidrag (refereegranskat)abstract
- This paper describes a design strategy towards a low power, DC level insensitive comparator with stable low power, level insensitive comparator with stable propagation time. The comparator b must suitable in applications were a constant propagation delay is critical, such as level crossing detection in ultrasound measurements and level crossing detection in ultrasound measurements and time quantization A/D convertem. The use of a long absolute propagation delay allows low power consumption while keeping the signal dependent propagation delay variation low. The comparator b able to process signals with all DC level within power rails due to a constant-gm, rail-to-rail, single-ended to differential converter implemented in the input stage. Schematic simulations show that the comparator has less than 1 ns delay variation at an absolute propagation delay of 12 ns. Test signals include frequencies from 0.5 MHz to 10 MHz, amplitudes fmm 30 mV to 1 V and all DC levels within rails.
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| 11. |
- Piper, Johan, et al.
(författare)
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A simulation model for embedding the transistor bias
- 2004
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Ingår i: [Host publication title missing]. - 0780385101 ; , s. 222-224
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Konferensbidrag (refereegranskat)abstract
- A simulation model for embedding the bias of a transistor is presented. The model exploits the simulator equilibrium point calculation to set the bias point of the transistor. The model uses negative feedback to set the bias point according to what the designer desires. When the simulator goes into its main analyses, the negative feedback is broken and embedded bias sources are added. This way it is possible to test an amplifier design before implementing the bias circuits. The model is technology independent and can be used on any kind of transistor
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| 12. |
- Signell, Svante, et al.
(författare)
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Radio design for future wireless SOC platforms : An overview
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - NEW YORK : IEEE. - 0780385101 ; , s. 277-280
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Konferensbidrag (refereegranskat)abstract
- As we move to third and fourth generation wireless providing higher data rates at shorter distances in "hotspots", future handhelds will be able to access different wireless infrastructures, e.g. UMTS and WLAN, from the same wireless device, be it a mobile phone, a PDA or a notebook. As a result SoC platforms for convergent 4G must address the challenge of increased complexity particularly as it pertains to the radio transceiver part of a chipset where power consumption and cost are the main differentiators. This paper presents an overview of the challenges faced in designing highly integrated radios in the context of 4G wireless communications. Aside from important issues such as multi antenna design and standards coexistence in the same SoC platform, we focus our overview on a few main thrusts that will be discussed in some details related to designing digitally programmable and con gurable ADCs, PLLs, analog baseband chains and RF front ends as well as techniques for packaging multi band radios and for achieving " rst pass" silicon success.
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| 13. |
- Strandberg, Roland, et al.
(författare)
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Analytical expression of the efficiency of phantom zero compensation applied on negative-feedback amplifiers
- 2004
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Ingår i: [Host publication title missing]. - 0780385101 ; , s. 87-90
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Konferensbidrag (refereegranskat)abstract
- This article reviews the phantom zero compensation technique, applied on negative-feedback (NFB) amplifiers, followed by an analysis of the important efficiency parameter, 0, of the implemented phantom zero. The effect of the efficiency on the root locus is presented, and it has been found that δ 7 will give near ideal behavior of the applied phantom zero. A reduced small signal model of the amplifier is presented along with a modified feedback factor, βph, which yields a simple analytical expression of the efficiency. The theory is independent of technology (BJT, FET, etc.), and exemplified on a two-stage BJT NFB amplifier. ©2004 IEEE.
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| 14. |
- Strandberg, Roland, et al.
(författare)
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Implementation of the signal component generator of a CALLUM 2 transmitter architecture in CMOS technology
- 2004
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Ingår i: [Host publication title missing]. - 0780385101 ; , s. 183-186
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Konferensbidrag (refereegranskat)abstract
- This article presents an analog implementation of the signal component generator (SCG) of the CALLUM2 linear transmitter architecture. The proposed SCG is suited for integration in a standard 0.35 μm CMOS process, and has from simulations proven to be adequate when operating on an EDGE modulated baseband signal with a data rate of 270.833 ksymb/s. The total current consumption of the SCG is 2.0 mA from a 3.3 V supply. A variable-gain amplifier (VGA) with common-mode (CM) control is presented, and the VGA is inserted in between the SCG and the voltage-controlled oscillator (VCO) to adjust the loop gain, which has strong influence on the stability and spectral performance of the linear transmitter architecture. © 2004 IEEE.
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| 15. |
- Vitkovski, Arsenij, et al.
(författare)
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Low-power and error coding for network-on-chip traffic
- 2004
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Ingår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS. - NEW YORK : IEEE. - 0780385101 ; , s. 20-23
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Konferensbidrag (refereegranskat)abstract
- The goals of this paper are to explore adaptability of low-power coding techniques, and estimate error coding overheads for Network-on-Chip (NoC) bus interconnections. Our simulations show that bus-invert encoding and partial bus invert encoding are not efficient due to their large overheads. On the other hand, implementation of error protection codes in the switch has only a small influence on both power consumption and time delay.
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