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1.	Abdulaziz, Mohammed, et al. (författare) A Compensation Technique for Two-Stage Differential OTAs 2014 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:8, s. 594-598 Tidskriftsartikel (refereegranskat)abstract In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values which makes it attractive for low power applications with low area overhead.
2.	Abdulaziz, Mohammed, et al. (författare) A Linearization Technique for Differential OTAs 2017 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 64:9, s. 1002-1006 Tidskriftsartikel (refereegranskat)abstract This brief presents an operational transconductance amplifier (OTA) linearization technique that is applied to a low-noise amplifier (LNA) and an OTA-C filter. Simulations show the effectiveness of the proposed technique on the LNA, whose noise and gain performance remain unaffected while the linearity is significantly improved. Measurements of the 80-MHz fourth order Butterworth OTA-C filter are also presented. It is implemented using six OTAs instead of eight, thus reducing the power consumption and area. The filter is implemented in 65-nm low-power CMOS, with a core area of 0.05 mm 2 and consumes 12.6 mA from 1.2 V supply. The measured in-band noise voltage is below 42 nV/ Hz‾‾‾√ , and the measured third order intercept point improvement using OTA linearization is up to 17 dB in-band and about 3 dB out-of-band. Supply and temperature variation measurements on three samples show that the linearization is effective without a need for bias adjustment.
3.	Afzal, Nadeem, et al. (författare) Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators 2014 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:9, s. 641-645 Tidskriftsartikel (refereegranskat)abstract In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.
4.	Akhlaghpasand, Hossein, et al. (författare) Jamming Suppression in Massive MIMO Systems 2020 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 67:1, s. 182-186 Tidskriftsartikel (refereegranskat)abstract In this brief, we propose a framework for protecting the uplink transmission of a massive multiple-input multiple-output (mMIMO) system from a jamming attack. Our framework includes a novel minimum mean-squared error-based jamming suppression (MMSE-JS) estimator for channel training and a linear zero-forcing jamming suppression (ZFJS) detector for uplink combining. The MMSE-JS exploits some intentionally unused pilots to reduce the pilot contamination caused by the jammer. The ZFJS suppresses the jamming interference during the detection of the legitimate users' data symbols. The proposed framework is implementable, since the complexities of computing the MMSE-JS and the ZFJS are linear (not exponential) with respect to the number of antennas at the base station and can be fabricated using 28-nm fully depleted silicon on insulator technology and for the mMIMO systems. Our analysis shows that the jammer cannot dramatically affect the performance of an mMIMO system equipped with the combination of MMSE-JS and ZFJS. Numerical results confirm our analysis.
5.	Andersson, Martin, et al. (författare) DT Modeling of Clock Phase Noise Effects in LP CT Delta-Sigma ADCs with RZ Feedback 2009 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 56:7, s. 530-534 Tidskriftsartikel (refereegranskat)abstract The performance of continuous-time (CT) Delta Sigma modulators is limited by their sensitivity to clock phase noise (PN). The clock PN-induced in-band noise (IBN) is dependent on the magnitude and frequency of both the desired in-band signals and the out-of-band signals, as well as the shape of the clock PN spectrum. This brief presents a discrete-time (DT) model of the dominant clock PN-induced errors. It enables fast and accurate simulations of the clock PN effects with arbitrary input signals, PN spectra, and noise-transfer functions. The model has been verified by CT simulations and measurements on a second-order low-pass CT Delta Sigma modulator with return-to-zero feedback. The flexibility and usefulness of the DT model are demonstrated, and the two dominant clock PN effects are compared by means of simulations with orthogonal frequency-division multiplexing input signals and various PN specifications.
6.	Andersson, Niklas, et al. (författare) A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture 2014 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:10, s. 773-777 Tidskriftsartikel (refereegranskat)abstract A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.
7.	Andreani, Pietro (författare) Some Results on Oscillation Stability in Multi-Mode Harmonic Oscillators 2023 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 70:3, s. 860-864 Tidskriftsartikel (refereegranskat)abstract We study the stability of oscillation in two different multi-mode harmonic oscillators by means of Barkhausen’s criterion, involving a minimum of mathematical machinery in favor of a more intuitive, circuit-based approach. The results of the theoretical analysis match very closely those obtained through transient simulations, confirming occasionally surprising outcomes of the latter.
8.	Angelov, Pavel, et al. (författare) A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers 2014 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:11, s. 860-864 Tidskriftsartikel (refereegranskat)abstract We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.
9.	Behmanesh, Baktash, et al. (författare) On the Calculation and Simulation of Loop Gain in Feedback Circuits 2023 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 70:11, s. 4033-4037 Tidskriftsartikel (refereegranskat)abstract We derive the expression of the loop gain in a circuit containing one or more feedback loops, where the transfer functions building the expression are found by means of a few AC analyses on the circuit. No approximations or assumptions on the nature of the loop or of the impedances therein contained are necessary. While hand calculations are certainly possible in the case of simpler circuits, the method is especially suitable for deployment in an analog circuit simulator environment.
10.	Bevilacqua, Andrea, et al. (författare) Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator 2012 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 59:1, s. 20-24 Tidskriftsartikel (refereegranskat)abstract The theoretical phase noise performance of a tuned-input tuned-output (TITO) oscillator is analyzed with a rigorous approach, which yields a compact closed-form phase noise equation that is dependent only on the value of the circuit components and current consumption of the oscillator. A straightforward comparison with the more commonly used differential LC-tank oscillator shows that the latter is in fact superior to the TITO oscillator, at least if the oscillator behavior is not too distant from the ideal behavior considered in the analysis. Phase noise simulations match admirably the theoretical results.
11.	Bhide, Ameya, et al. (författare) An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS 2013 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 60:7, s. 387-391 Tidskriftsartikel (refereegranskat)abstract This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.
12.	Bhide, Ameya, et al. (författare) Effect of Clock Duty-Cycle Error on Two-Channel Interleaved Delta Sigma DACs 2015 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 62:7, s. 646-650 Tidskriftsartikel (refereegranskat)abstract Time-interleaved delta-sigma (Delta Sigma) modulation digital-to-analog converters (TIDSM DACs) have the potential for a wideband operation. The performance of a two-channel interleaved Delta Sigma DAC is very sensitive to the duty cycle of the half-rate clock. This brief presents a closed-form expression for the signal-to-noise-plus-distortion ratio (SNDR) loss of such DACs due to a duty-cycle error for modulators with a noise transfer function of (1 - z(-1))(n). Adding a low-order finite-impulse-response filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. These expressions are useful for choosing a suitable modulator and filter order for an interleaved Delta Sigma DAC in the early stage of the design process.
13.	Castañeda, Oscar, et al. (författare) High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO with Processing-in-Memory 2020 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 67:5, s. 891-895 Tidskriftsartikel (refereegranskat)abstract All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is challenging as traditional baseband processing would result in excessively high power consumption and large silicon area. The recently-proposed concept of finite-alphabet equalization is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware. In this brief, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of multiply-accumulate (MAC) units and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital VLSI implementation results in 28nm CMOS show that the bit-serial PIM architecture reduces the area and power consumption up to a factor of 2× and 3×, respectively, when compared to a parallel MAC array that operates at the same throughput.
14.	Chani Cahuana, Jessica, 1988, et al. (författare) Digital Predistortion Parameter Identification for RF Power Amplifiers Using Real-Valued Output Data 2017 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 64:10, s. 1227-1231 Tidskriftsartikel (refereegranskat)abstract This brief presents a novel digital predistortion (DPD) parameter identification technique that requires only the acquisition of either the in-phase (I) or the quadrature (Q) component of the power amplifier (PA) output signal. To this end, an approach that allows us to estimate the parameters of a model using only one of the IQ components of the model output is presented. Based on experimental results, it is shown that the proposed real-valued measurements based technique can offer similar linearization capabilities as its complex-valued counterparts. The experimental results also indicate that the proposed technique can be used in combination with other techniques that focus on reducing the speed of analog-to-digital converters (ADCs)
15.	Chen, Hui, et al. (författare) Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation 2020 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 67:11, s. 2652-2656 Tidskriftsartikel (refereegranskat)abstract We present a CORDIC (Coordinate Rotation Digital Computer)-based method to compute the logarithm function with base 2 and validate this method by software simulation and hardware implementation. Technically, we overcome the limitation of traditional hyperbolic CORDIC and transform it based on the idea of generalized hyperbolic CORDIC so that it can be used to compute $log_{2}x\;(x\;\epsilon \;[1,2))$ . The proposed method requires only simple shift-and-add operations and has a great tradeoff between precision (or speed) and area. In MATLAB, we provide different precisions corresponding to the iterations of the transformed CORDIC for user needs. Using a pipelined structure and setting the number of iterations to be 16 (the average relative error is $2.09\times 10<^>{-6}$ ), we implement an example hardware circuit. Synthesized under the SMIC 65nm CMOS technology, the circuit has an area of 24100 $\mu m<^>{2}$ and computation time of 11.1 ns, which can save 31.04x0025; area and improve 6.92x0025; computation speed averagely compared with existing methods.
16.	Deng, Mingxin, et al. (författare) Efficient Parallel Polynomial-Based Compensation Structure for Frequency Response Mismatch in Two-Channel TI-ADCs 2024 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 71:2, s. 992-996 Tidskriftsartikel (refereegranskat)abstract This brief introduces a compensation structure for frequency response mismatch (FRM) errors in two-channel time-interleaved analog-to-digital converters (TI-ADCs) based on polynomial models of the channel frequency responses. It can be used for any Nyquist band and it comprises parallel error approximation branches (EABs), each branch consisting of a fixed differentiator of unique degree cascaded with a variable multiplier and a simple modulator. It suffices to alter the variable multipliers when the channels change, thereby avoiding online filter design. In addition, it achieves a lower latency and a significantly lower computational complexity compared to cascaded polynomial-based structures. Numerical simulations and comparisons are included, validating the efficacy of the proposed structure.
17.	Eghbali, Amir, et al. (författare) Design of Modulated Filter Banks and Transmultiplexers With Unified Initial Solutions and Very Few Unknown Parameters 2015 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 62:4, s. 397-401 Tidskriftsartikel (refereegranskat)abstract This brief proposes a method for designing modulated filter banks (FBs) with a large number of channels. The impulse response of the long prototype filter is parameterized in terms of a few short impulse responses, thus significantly reducing the number of unknown parameters. The proposed method starts by first obtaining an FB with a few channels. The solution of this FB is then partly reused as an initial (very close to final) solution in the design of FBs with a large number of channels. The number of unknown parameters hence drastically reduces. For example, we can first design a cosine modulated FB (CMFB) with three channels whose prototype filter has a stopband attenuation of about 40 dB. We can then reuse the solution of this CMFB in the design of a CMFB with 16 384 channels whose prototype filter has a similar stopband attenuation. With our proposed method, we need to reoptimize only 14 parameters to design the CMFB with 16 384 channels.
18.	Farjam, Tahmoores, et al. (författare) A timer-based distributed channel access mechanism in networked control systems 2018 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 65:5, s. 652-656 Tidskriftsartikel (refereegranskat)abstract We consider a system consisting of multiple heterogeneous control subsystems sharing a common communication resource for accomplishing their control tasks. Despite the numerous advantages that such networked control systems (NCSs) offer, their implementation is limited in practice due to the limited communication resources. We propose a novel distributed approach for the resource allocation problem in NCSs by which the subsystems can coordinate to access the network. More specifically, we develop a deterministic distributed scheme with which the subsystem with the highest cost is selected, based only on local information without requiring explicit communication between the subsystems. The efficiency of our scheme is demonstrated via simulations and it is compared with a centralized approach and other relevant approaches.
19.	Fernandez-Prieto, Armando, et al. (författare) Glide Symmetry Applied to the Design of Common-Mode Rejection Filters Based on Complementary Split-Ring Resonators 2023 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 70:6, s. 1911-1915 Tidskriftsartikel (refereegranskat)abstract In this brief, glide symmetry is applied to design common-mode rejection filters based on defected ground structures with bandstop response. To this aim, complementary split-ring resonators are chosen as the basic components for common-mode rejection. To illustrate the advantages of using glide symmetry, three implementations are studied and compared. The results reveal that glide symmetry offers the best performance in terms of common-mode rejection level and fractional bandwidth. Furthermore, glide symmetry barely affects the integrity of the differential mode. A prototype of each of the considered symmetries has been designed, simulated, and tested for practical validation. Good agreement is observed between the simulated and measured results, experimentally demonstrating the advantages of glide symmetry.
20.	Fritzin, Jonas, et al. (författare) Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS 2012 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 59:11, s. 726-730 Tidskriftsartikel (refereegranskat)abstract This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and +29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.
21.	Fritzin, Jonas, et al. (författare) Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS 2011 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 58:10, s. 642-646 Tidskriftsartikel (refereegranskat)abstract This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.
22.	Gangarajaiah, Rakesh, et al. (författare) A Digitally Assisted Non-Linearity Mitigation System for Tunable Channel Select Filters 2016 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 63:1, s. 69-73 Tidskriftsartikel (refereegranskat)abstract This brief presents a low-complexity system for digitally assisting a channel select filter (CSF) to mitigate both even- and odd-order nonlinearities. The proposed solution is scalable and can be utilized for nonlinearity mitigation in different analog transceiver blocks. The system consists of an auxiliary path with a low-resolution analog to digital converter (ADC) enabling digital recreation and measurement of the distortion in the main path and relies on an adaptive digital signal processing algorithm to detect and tune the analog components to their optimal settings. The system provides robustness against process, voltage, and temperature variations, and the digital part requires an equivalent logic of only 42 k gates in CMOS technology, enabling cost-efficient implementation on integrated circuits. The operation of the system has been verified by using a tunable CSF capable of receiving a 10-MHz baseband signal interfaced to an external ADC. The results demonstrate that the proposed system is capable of tuning the CSF to its optimal bias voltage, providing a third-order intermodulation reduction of 14.5 dB.
23.	Garrido Gálvez, Mario, et al. (författare) A Serial Commutator Fast Fourier Transform Architecture for Real-Valued Signals 2018 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 65:11, s. 1693-1697 Tidskriftsartikel (refereegranskat)abstract This brief presents a novel pipelined architecture to compute the fast Fourier transform of real input signals in a serial manner, i.e., one sample is processed per cycle. The proposed architecture, referred to as real-valued serial commutator, achieves full hardware utilization by mapping each stage of the fast Fourier transform (FFT) to a half-butterfly operation that operates on real input signals. Prior serial architectures to compute FFT of real signals only achieved 50% hardware utilization. Novel data-exchange and data-reordering circuits are also presented. The complete serial commutator architecture requires 2 log(2) N - 2 real adders, log(2) N - 2 real multipliers, and N + 9 log(2) N - 19 real delay elements, where N represents the size of the FFT.
24.	Garrido Gálvez, Mario, et al. (författare) Accurate Rotations Based on Coefficient Scaling 2011 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 58:10, s. 662-666 Tidskriftsartikel (refereegranskat)abstract This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.
25.	Garrido Gálvez, Mario, et al. (författare) CORDIC II: A New Improved CORDIC Algorithm 2016 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 63:2, s. 186-190 Tidskriftsartikel (refereegranskat)abstract In this brief, we present the CORDIC II algorithm. Like previous CORDIC algorithms, the CORDIC II calculates rotations by breaking down the rotation angle into a series of microrotations. However, the CORDIC II algorithm uses a novel angle set, different from the angles used in previous CORDIC algorithms. The new angle set provides a faster convergence that reduces the number of adders with respect to previous approaches.
26.	Garrido Gálvez, Mario, et al. (författare) Optimum Circuits for Bit Reversal 2011 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 58:10, s. 657-661 Tidskriftsartikel (refereegranskat)abstract This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.
27.	Garrido Gálvez, Mario (författare) The Feedforward Short-Time Fourier Transform 2016 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 63:9, s. 868-872 Tidskriftsartikel (refereegranskat)abstract This brief presents the feedforward short-time Fourier transform (STFT). This new approach is based on reusing the calculations of the STFT at consecutive time instants. This leads to significant savings in hardware components with respect to fast Fourier transform based STFTs. Furthermore, the feedforward STFT does not have the accumulative error of iterative STFT approaches. As a result, the proposed feedforward STFT presents an excellent tradeoff between hardware utilization and performance.
28.	Garrido Gálvez, Mario, et al. (författare) The Serial Commutator FFT 2016 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 63:10, s. 974-978 Tidskriftsartikel (refereegranskat)abstract This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.
29.	Garrido, Mario, 1981- (författare) Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal 2019 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 66:4, s. 657-661 Tidskriftsartikel (refereegranskat)abstract This brief presents novel circuits for calculating the bit reversal on parallel data. The circuits consist of delays/memories and multiplexers, and have the advantage that they requires the minimum number of multiplexers among circuits for parallel bit reversal so far, as well as a small total memory.
30.	Haque, Muhammad Fahim Ul, et al. (författare) Aliasing-Compensated Polar PWM Transmitter 2017 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE. - 1549-7747 .- 1558-3791. ; 64:8, s. 912-916 Tidskriftsartikel (refereegranskat)abstract This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.
31.	Harikumar, Prakash, et al. (författare) A 0.4 V, sub-nW, 8-bit 1 kS/s SAR ADC in 65 nm CMOS for Wireless Sensor Applications 2016 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. - 9781479998777 ; 63:8, s. 743-747 Tidskriftsartikel (refereegranskat)abstract This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS and uses a supply voltage of 0.4 V. In order to achieve sufficient linearity, a two-stage charge pump was implemented to boost the gate voltage of the sampling switches. A custom-designed unit capacitor of 1.9 fF was used to realize the capacitive digital-to-analog converters. The ADC achieves an effective number of bits of 7.81 bits while consuming 717 pW and attains a figure of merit of 3.19 fJ/conversion-step. The differential nonlinearity and the integral nonlinearity are 0.35 and 0.36 LSB, respectively. The core area occupied by the ADC is only 0.0126 mm2.
32.	Hausmair, Katharina, 1982, et al. (författare) Multiplierless implementation of an aliasing-free digital pulsewidth modulator 2013 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 60:9, s. 592-596 Tidskriftsartikel (refereegranskat)abstract Digital pulsewidth modulators are used to transform nonconstant amplitude signals into pulsed signals, such that the information lying in the signal amplitude is encoded in the widths of pulses. Because of the inherent aliasing distortion in digital pulsewidth-modulated signals, additional signal processing steps are required to make pulsewidth modulation (PWM) suitable for applications like digital audio amplification or burst-mode radio-frequency transmitters. These processing steps, however, entail an undesirable increase in computational effort. This brief presents a multiplierless implementation of a digital aliasing-free pulsewidth modulator using lookup tables, adders, and arithmetic shifts only. Mathematical equations of asymmetric double-edge PWM are given, as well as a modified aliasing-free version of this PWM technique that directly integrates the distortion-avoiding signal processing steps into the pulsewidth modulator. Based on these equations, a multiplierless implementation of the aliasing-free PWM (AF-PWM) is developed. Simulation results obtained with a Simulink fixed-point model show that the proposed modulator implementation provides a feasible solution for realizing AF-PWM with low computational effort.
33.	Hermanowicz, E., et al. (författare) A fractionally delaying complex Hilbert transform filter 2008 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 55:5, s. 452-456 Tidskriftsartikel (refereegranskat)abstract In this paper, we present a novel complex discrete-time filter. This is a fractionally delaying (FD) Hilbert transform filter (HTF) further called the FD HTF. The filter is based on a pair of rotated variable fractional delay (VFD) filters. It is capable of performing the Hilbertian as well as VFD filtering of the incoming discrete-time signal at the same time. Thus, one can substitute a cascade of the HTF and the VFD filters with an aggregated filter proposed here. The technique is simple to implement. The advantages lie in lower total delay introduced by the compound filter and in a modular structure. The rotated VFD filters in the pair differ only in the value of one parameter-the VFD. The proposed FD HTF can be applied to adaptive quadrature sub-sample estimation of delay. © 2008 IEEE.
34.	Horestani, Fatemeh Karami, et al. (författare) Ultra-High-Resistance Pseudo-Resistors with Small Variations in a Wide Symmetrical Input Voltage Swing 2023 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE. - 1549-7747 .- 1558-3791. ; 70:8, s. 2794-2798 Tidskriftsartikel (refereegranskat)abstract This paper presents a new strategy and circuit configuration composed of serially-connected PMOS devices operating in the subthreshold region for implementing ultra-highvalue resistors required in very low-frequency active-RC filters and bio-amplifiers. Depending on the application, signal bandwidth for instance in bio-amplifiers may vary from a few mHz up to a maximum of 10 kHz. Three different resistor structures are proposed to achieve ultra-high resistance. While ranging in the order of several TY, the proposed ultra-high-resistance pseudoresistors occupy a small on-chip silicon area, which is one of the main issues in the design of analog front-end circuits in ultra-low power implantable biomedical microsystems. In addition, these ultra-high-value resistors lead to the use of a small capacitance to create a very small cut-off frequency. Therefore, the large area to implement capacitances is also considerably reduced. The proposed resistor structures have very small variations about 7% and 12% in a wide input voltage range (-0.5 V +0.5 V), thus significantly improving the total harmonic distortion of bioamplifiers and the analog front-end of the system. Simulation results of different circuits designed in a 180nm CMOS technology, are shown to demonstrate the advantages of the proposed ultra-high-resistance pseudo-resistors.
35.	Huang, Yu-Kai, et al. (författare) A Current Monitoring and Over-Current Detection Circuit for Safe Electrical Stimulation 2023 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 70:5, s. 1684-1688 Tidskriftsartikel (refereegranskat)abstract This brief presents an integrated solution to over-current protection in neuromuscular stimulators. The proposed approach provides fast detection of a single-fault condition, i.e., unintentional electrode short circuit or malfunction of the stimulator, thereby preventing prolonged high-intensity currents from flowing into tissues. In addition, a programmable current threshold enables the system to be also used for monitoring the stimulation intensity. The proposed solution was designed in a 180 nm high-voltage CMOS technology, and its functionality was verified by post-layout simulations in which the safety mechanisms were tested under fault conditions. The implementation only occupies an area of 0.286 mm2, making it feasible to be embedded in fully integrated NMES stimulators while providing the required patient safety.
36.	Jakobsson, Anders, et al. (författare) A Low Noise RC-based Phase Interpolator in 16-nm CMOS 2019 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 66:1 Tidskriftsartikel (refereegranskat)abstract This paper describes a passive analog phase interpolator, utilizing a switched RC-network. The proposed circuit eliminates the current sources in a phase interpolator based on constant-slope charging. By eliminating the current source, the noise is significantly reduced due to the reduction in thermal and flicker noise. The phase interpolator has a resolution of 6 bits and is implemented in a 16-nm CMOS process. The maximum differential non-linearity is measured to be 0.1 LSBs at a 192 ps input time delta. The circuit draws 0.2 mW from a 0.8 V supply, and occupies 0.004 mm2.
37.	Johansson, Håkan, et al. (författare) A Least-Squares Filter Design Technique for the Compensation of Frequency Response Mismatch Errors in Time-Interleaved A/D Converters 2008 Ingår i: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS. - 1549-7747. ; 55:11, s. 1154-1158 Tidskriftsartikel (refereegranskat)abstract This paper introduces a least-squares filter design technique for the compensation of frequency response mismatch errors in M-channel time-interleaved analog-to-digital converters. The overall compensation system is designed by determining M filter impulse responses analytically through M separate matrix inversions. The proposed technique offers an alternative to least-squares techniques that determine all filters simultaneously. Several design examples are included for illustration.
38.	Johansson, Håkan (författare) Fractional-Delay and Supersymmetric Mth-Band Linear-Phase FIR Filters Utilizing Partially Symmetric and Antisymmetric Impulse Responses 2012 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 59:6, s. 366-370 Tidskriftsartikel (refereegranskat)abstract This brief considers fractional-delay finite-length impulse response (FIR) filters and a class of supersymmetric Mth-band linear-phase FIR filters utilizing partially symmetric and partially antisymmetric impulse responses. Design examples reveal significant multiplication savings, depending on the specification, as compared to traditional filters.
39.	Johansson, Håkan, et al. (författare) Two-Stage-Based Polyphase Structures for Arbitrary-Integer Sampling Rate Conversion 2015 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 62:5, s. 486-490 Tidskriftsartikel (refereegranskat)abstract This brief derives efficient two-stage-based polyphase structures for arbitrary-integer sampling rate conversion. For even-integer conversions, the overall structures correspond to parallelized conventional two-stage structures, but the derivations in this brief offer further insights when comparing the two cases of odd-and even-integer conversions. For the class of linear-phase finite-length impulse response Mth-band filters, it is then demonstrated through design examples that conversions by odd factors are in fact more efficient than by even factors.
40.	Jonsson, Fredrik, et al. (författare) A low-leakage open-loop frequency synthesizer allowing small-area on-chip loop filter 2009 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 56:3, s. 195-199 Tidskriftsartikel (refereegranskat)abstract A frequency synthesizer targeting low-power packet-based frequency-shift-keying (FSK) applications using open-loop modulation of the oscillator is presented. Unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. It is, therefore, possible to use a wide loop-filter bandwidth without violating the noise or spurious requirements. A wideband loop-filter can be implemented using small component values, allowing an on-chip loop filter. To handle the frequency drift associated with open-loop implementations, a low-leakage charge pump is proposed. The synthesizer is implemented using a 0.18-mu m CMOS process. The total power consumption is 9 mW, and the circuit area including the voltage-controlled oscillator (VCO) inductors and on-chip loop-filter is 0.32 mm(2). The measured frequency drift indicates a leakage current of below 2 fA.
41.	Kamuf, Matthias, et al. (författare) Survivor path processing in Viterbi decoders using register exchange and traceforward 2007 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 54:6, s. 537-541 Tidskriftsartikel (refereegranskat)abstract This paper proposes a new class of hybrid VLSI architectures for survivor path processing to be used in Viterbi decoders. The architecture combines the benefits of register exchange and trace-forward algorithms, that is, low memory requirement and latency versus implementation efficiency. Based on a structural comparison, it becomes evident that the architecture can be efficiently applied to codes with a larger number of states where usually trace-back-based architectures, which increase latency, are dominant.
42.	Kumm, Martin, et al. (författare) Optimal Single Constant Multiplication Using Ternary Adders 2018 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 65:7, s. 928-932 Tidskriftsartikel (refereegranskat)abstract The single constant coefficient multiplication is a frequently used operation in many numeric algorithms. Extensive previous work is available on how to reduce constant multiplications to additions, subtractions, and bit shifts. However, on previous work, only common two-input adders were used. As modern field-programmable gate arrays (FPGAs) support efficient ternary adders, i.e., adders with three inputs, this brief investigates constant multiplications that are built from ternary adders in an optimal way. The results show that the multiplication with any constant up to 22 bits can be realized by only three ternary adders. Average adder reductions of more than 33% compared to optimal constant multiplication circuits using two-input adders are achieved for coefficient word sizes of more than five bits. Synthesis experiments show FPGA average slice reductions in the order of 25% and a similar or higher speed than their two-input adder counterparts.
43.	Liu, Xiangyu, et al. (författare) Correlation-Based Calibration for Nonlinearity Mismatches in Dual-Channel TIADCs 2020 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 67:3, s. 585-589 Tidskriftsartikel (refereegranskat)abstract Mismatches affect the dynamic performance of time-interleaved analog-to-digital converters (TIADCs). Linear mismatches can be calibrated by many mature methods, but if higher performance is required, nonlinearity mismatches have to be suppressed. The background calibration method based on input-free band (IFB) functions poorly for narrow-band signals. This brief proposes a correlation-based calibration method for nonlinearity mismatches in dual-channel TIADCs which behaves well for both wide-band and narrow-band signals. The output samples are calibrated by reducing the residual distortions which are approximated by multiplying the pseudo distortions and the estimated mismatch coefficients. The pseudo distortions are acquired by using a frequency-shifter, a differentiator, and multipliers. The coefficients which indicate the mismatch strength are estimated by eliminating the cross-correlation of the calibrated output samples and the calibrated pseudo distortions at zero lag. Simulations show that the proposed method can improve the SFDR by dozens of dBc for narrow-band input signals, compared with the IFB method. For the 16-QAM signal, the error vector magnitude improvement over the IFB method is 35.48 dB.
44.	Lu, Ping, et al. (författare) A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration 2016 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; , s. 1019-1023 Tidskriftsartikel (refereegranskat)abstract This paper presents a 2-dimension (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated-ring-oscillators (GROs) in the X/Y Vernier branches. The already small Vernier quantization noise (~10.6ps) is improved by the 1st-order noise shaping of the GRO. Moreover, since all delay differences between X phases and Y phases can be used (rather than only the diagonal line of the 1-dimension architecture), the intrinsic large latency time of the Vernier architecture is dramatically reduced. The TDC is implemented in a 65nm CMOS process and consumes 2.3mA from 1.0V. The measured total noise integrated over a bandwidth of 1.25 MHz yields an equivalent TDC resolution of 2.2ps, while the average latency time (within 2ns) is less than 1/6 of that in a standard Vernier TDC.
45.	Mao, Jia, et al. (författare) A Subgigahertz UWB Transmitter With Wireless Clock Harvesting for RF-Powered Applications 2014 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 61:5, s. 314-318 Tidskriftsartikel (refereegranskat)abstract A subgigahertz ultrawideband (UWB) transmitter (TX) with wireless clock harvesting is presented for RF-powered applications such as RF identifications and implantable devices in the 180-nm CMOS process. The proposed low-power TX consists of a harmonic injection-locked ring oscillator (ILRO), a synchronized pulse generator, and a driver stage. Through wireless injection locking, a 450-MHz carrier is extracted using the sub-harmonic of an ultrahigh frequency signal radiated by a reader. Following the ILRO, the carrier is gated and amplified to generate the UWB pulses. This approach avoids power-hungry frequency synthesis circuitry and bulky crystal reference, and it relaxes the timing synchronization between the reader and the tag. Due to aggressive duty cycling and the fast setup time (< 50 ns at an input power of -15 dBm), the proposed TX is power scalable with an energy consumption of 35 pJ/pulse. To comply with the Federal Communications Commission regulations, the maximum pulse rate is up to 5 MHz with a peak-to-peak pulse amplitude of 0.75 V and a corresponding power consumption of 175 mu W, which is favorable to RF-powered applications.
46.	Mao, Jia, et al. (författare) A UWB-Based Sensor-to-Time Transmitter for RF-Powered Sensing Applications 2016 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE Press. - 1549-7747 .- 1558-3791. ; 63:5 Tidskriftsartikel (refereegranskat)abstract An ultrawideband (UWB)-based sensor-to-time transmitter consisting of a remote control (RC) time-constant interface and an ultralow-power pulse generator is presented. The sensing information is directly extracted and transmitted in the time domain, exploiting UWB pulses with a high time-domain resolution. This approach eliminates the need for an analog-to-digital converter and baseband blocks of sensor tags; meanwhile, it reduces the number of bits to be transmitted for energy saving. The sensor interface measures the discharging time of the RC time constant proportional to the sensor variation. The UWB pulses are triggered with intervals of the RC discharging time, without any digitizing or modulations. The circuit prototype is implemented in the standard 0.18-mu m CMOS process. Resistance measurement results show that the proposed system exhibits an effective number of resolution bits (ENOB) of 7.7 bits with an average relative error of 0.42% in the range of 200-1500 Omega. The overall energy consumption of conversion and transmission per sample is measured to be 0.58 nJ with a 1.27-Vp-p pulse amplitude, which is favorable to radio-frequency-powered wireless sensing applications.
47.	Martins, W. A., et al. (författare) Oversampled DFT-Modulated Biorthogonal Filter Banks : Perfect Reconstruction Designs and Multiplierless Approximations 2020 Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747. ; 67:11, s. 2777-2781 Tidskriftsartikel (refereegranskat)
48.	Mishra, Deepak, 1990-, et al. (författare) Charging time characterization for wireless RF energy transfer 2015 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 62:4, s. 362-366 Tidskriftsartikel (refereegranskat)abstract Wireless energy transfer to the onboard energy storage element using dedicated radio frequency (RF) energy source has the potential to provide sustained network operations by recharging the sensor nodes on demand. To determine the efficiency of RF energy transfer (RFET), characterization of recharging process is needed. Different from classical capacitor-charging operation, the incident RF waves provide constant power (instead of constant voltage or current) to the storage element, which requires a new theoretical framework for analyzing the charging behavior. This work develops the charging equation for replenishing an energy-depleted storage element by RFET. Since the remaining energy on a sensor node is a random parameter, the RF charging time distribution for a given residual voltage distribution is also derived. The analytical model is validated through hardware experiments and simulations.
49.	Muralidharan Pillai, Anu Kalidas, 1980-, et al. (författare) Prefilter-Based Reconfigurable Reconstructor for Time-Interleaved ADCs With Missing Samples 2015 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE Press. - 1549-7747 .- 1558-3791. ; 62:4, s. 392-396 Tidskriftsartikel (refereegranskat)abstract This brief proposes a reconstruction scheme for the compensation of frequency-response mismatch errors at the output of a time-interleaved analog-to-digital converter (TI-ADC) with missing samples. The missing samples are due to sampling instants reserved for estimating the channel mismatch errors in the TI-ADC. Compared with previous solutions, the proposed scheme offers substantially lower computational complexity.
50.	Onet, Raul, et al. (författare) High-Purity and Wide-Range Signal Generator for Bioimpedance Spectroscopy 2018 Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 65:12, s. 1884-1888 Tidskriftsartikel (refereegranskat)abstract This brief presents an integrated high-purity current signal generator (SG), part of a bioimpedance spectroscopy system that performs measurements in the frequency range from 1 kHz to 2 MHz, and it is able to measure bioimpedance values from 100 Omega to 1 M Omega. The SG is implemented in a 0.18-mu m CMOS process, it is powered by a single 1.8 V voltage source, and occupies a total area of 1.62 mm(2). It is able to generate single-frequency signals from 1 kHz to 2 MHz in 12 steps logarithmically spaced. High signal purity is achieved by using a second-order low-pass filter, with a bandwidth that can be programmed from 4 kHz to 8 MHz, in 12 points logarithmically spaced. The SG's power consumption varies from 750 mu W, at the lowest frequencies and gain, to 2.06 mW at the highest frequencies and gain. The output current levels can be modified from 130 nA up to 10 mu A in five programmable steps (9.5 dB per step). The SG achieves a spurious-free dynamic range larger than 40 dB while covering almost three decades in frequency. Such performance enables measurements with errors below 1%, as it is required for accurate bioimpedance measurements in many medical applications.

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