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1.
  • Strak, Adam, et al. (författare)
  • Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits
  • 2008
  • Ingår i: IEEE Transactions on Circuits And Systems Part I. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7122 .- 1558-1268 .- 1549-8328 .- 1558-0806. ; 55:4, s. 1041-1054
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.
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2.
  • Abbas, Muhammad, et al. (författare)
  • On the Fixed-Point Implementation of Fractional-Delay Filters Based on the Farrow Structure
  • 2013
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:4, s. 926-937
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, the fixed-point implementation of adjustable fractional-delay filters using the Farrow structure is considered. Based on the observation that the sub-filters approximate differentiators, closed-form expressions for the L-2-norm scaling values at the outputs of each sub-filter as well as at the inputs of each delay multiplier are derived. The scaling values can then be used to derive suitable word lengths by also considering the round-off noise analysis and optimization. Different approaches are proposed to derive suitable word lengths including one based on integer linear programming, which always gives an optimal allocation. Finally, a new approach for multiplierless implementation of the sub-filters in the Farrow structure is suggested. This is shown to reduce register complexity and, for most word lengths, require less number of adders and subtracters when compared to existing approaches.
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3.
  • Andersson, Rikard, et al. (författare)
  • Using Rotator Transformations to Simplify FFT Hardware Architectures
  • 2020
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 67:12, s. 4784-4793
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.
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4.
  • Bruni, Giovanni, 1989, et al. (författare)
  • DPTC - An FPGA-Based Trace Compression
  • 2020
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 67:1, s. 189-197
  • Tidskriftsartikel (refereegranskat)abstract
    • Recording of flash-ADC traces is challenging from both the transmission bandwidth and storage cost perspectives. This work presents a configuration-free lossless compression algorithm, which addresses both limitations, by compressing the data on-the-fly in the controlling FPGA. Thus it can easily be used directly in front-end electronics. The method first computes the differences between consecutive samples in the traces, thereby concentrating the most probable values around zero. The values are then stored as groups of four, with only the necessary least-significant bits in a variable-length code, packed in a stream of 32-bit words. To evaluate the efficiency, the storage cost of compressed traces is modeled as a baseline cost including ADC noise, and a cost for pulses that depends on amplitude and width. The free parameters and the validity of the model are determined by compressing artificial traces with varying characteristics. The compression method was also applied to actual data from different types of detectors. A typical storage cost is around 4 to 5 bits per sample. Code for the FPGA implementation in VHDL and for the CPU decompression routine in C are available as open source software, both able to operate at speeds of 400 Msamples/s.
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5.
  • Buonomo, Antonio, et al. (författare)
  • A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation
  • 2013
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:12, s. 3126-3135
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper proposes a simple and effective modification of the conventional divide-by-two injection locked frequency divider (ILFD) with direct-injection aimed at allowing both the divide-by-two and the divide-by-three modes of operation. The proposed circuit does not employ additional inductors as usual in divide-by-three ILFDs, but exploits the combined effect of two independent injection techniques. The resulting locking range for the divide-by-three mode is comparable in size to that for the divide-by-two. Thus, the proposed circuit can be an optimum alternative to existing dividers, due to the flexibility of two division ratios and due to the absence of additional inductors. An intuitive explanation of the locking mechanism underlying this ILFD and a quantitative analysis are provided, allowing one to predict the amplitude and phase of oscillation in the locked mode, as well as the locking range, with approximate closed-form expressions. Measurements on a circuit prototype and results from SPICE simulations demonstrate the effectiveness of the circuit and validate the theoretical model and the resulting formulas.
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6.
  • Chen, H., et al. (författare)
  • Huicore : A Generalized Hardware Accelerator for Complicated Functions
  • 2022
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 69:6, s. 2463-2476
  • Tidskriftsartikel (refereegranskat)abstract
    • Emerging advanced System-on-Chip (SoC) designs contain more and more complicated functions to be accelerated. This presents a challenge to conventional design approaches which use different hardware architectures or separate hardware accelerators to implement the various functions. To tackle this challenge, for the first time, we propose a generalized hardware accelerator called 'Huicore' to speed up diverse functions on the same substrate. Through the analysis and transformation of mathematical characteristics, we reveal the commonality of many complicated functions using the CORDIC algorithm. Then we explore a reconfigurable architecture to implement them. The proposed reconfigurable accelerator can not only accelerate the implementation of many complicated functions, but also has small area, low power consumption and high precision. It is very suitable for integration in a SoC system to accelerate the implementation of various applications.
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7.
  • Chen, Hui, et al. (författare)
  • Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers
  • 2021
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 68:8, s. 3293-3304
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper proposes a low-complexity method and architecture to compute the logarithm of complex numbers based on coordinate rotation digital computer (CORDIC). Our method takes advantage of the vector mode of circular CORDIC and hyperbolic CORDIC, which only needs shift-add operations in its hardware implementation. Our architecture has lower design complexity and higher performance compared with conventional architectures. Through software simulation, we show that this method can achieve high precision for logarithm computation, reaching the relative error of 10(-7). Finally, we design and implement an example circuit under TSMC 28nm CMOS technology. According to the synthesis report, our architecture has smaller area, lower power consumption, higher precision and wider operation range compared with the alternative architectures.
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8.
  • Chen, Hui, et al. (författare)
  • Symmetric-Mapping LUT-Based Method and Architecture for Computing X-Y-Like Functions
  • 2021
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 68:3, s. 1231-1244
  • Tidskriftsartikel (refereegranskat)abstract
    • We propose a new method and hardware architecture to compute the functions expressed as XY ( X and Y are arbitrary floating-point numbers), which can support arbitrary Nth root, exponential and power operations. Because of the complexity of direct computation, we usually convert it to logarithm, multiplication, and antilogarithm operations. Traditional approaches suffer from long latency, large area and high power consumption. To solve this problem, we propose a symmetric-mapping lookup table (SM-LUT) to be capable of computing log(2) x (x is an element of [1, 2]) and 2 x (x is an element of [0, 1]) simultaneously. It lays the foundation for computing XY. To further improve hardware performance of our architecture, we propose a multi-region address searcher to speed up the calculation of SM-LUT. In addition, we use an optimized Vedic multiplier to shorten the critical path and improve the efficiency of multiplication, which is included in computing X-Y. Under the TSMC 40nm CMOS technology, we design and synthesize a reference circuit to compute X-Y with a maximum relative error of 10(-3). The report shows that the reference circuit achieves the area of 14338.50 mu m(2) and the power consumption of 4.59 mW at the frequency of 1 GHz. In comparison with the state-of-the-art work under the same input range and similar precision, it saves 78.57% area and 80.42% power consumption for (N)root R computation and 82.89% area and 81.89% power consumption for R-N computation averagely. On top of that, our architecture reduces the computation latency by 62.77% averagely and has one more order of magnitude of energy efficiency than others.
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9.
  • Chen, J., et al. (författare)
  • Distributed Control of Multi-Functional Grid-Tied Inverters for Power Quality Improvement
  • 2021
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers Inc.. - 1549-8328 .- 1558-0806. ; 68:2, s. 918-928
  • Tidskriftsartikel (refereegranskat)abstract
    • Multi-functional grid-tied inverters (MFGTIs) have been investigated recently for improving the power quality (PQ) of microgrids (MGs) by exploiting the residual capacity (RC) of distributed generators. Several centralized and decentralized methods have been proposed to coordinate the MFGTIs. However, with the increasing number of the MFGTIs, it demands a method with improved reliability and flexibility, which are characteristics of distributed framework that has not been introduced into the PQ improvement (PQI) field before. In this paper, we propose a distributed consensus method to undertake the PQI task. The task is proportionally shared among the MFGTIs according to their instant RCs. Besides, most of the existing methods assume that the RCs of the MFGTIs are sufficient for tackling the PQ problem (PQP), which is not always true. In the case of insufficient RC, the active power output of each MFGTI is scaled down by the same factor determined by a proposed leader-follower protocol to make room for the task. In summary, the PQP is dealt with in both cases of sufficient and insufficient RC under the distributed control framework. Finally, simulations and hardware-in-the-loop experiments of an MG consisting of three 10kVA MFGTIs are presented to verify the effectiveness of the proposed methods. © 2004-2012 IEEE.
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10.
  • Chen, Sau-Gee, et al. (författare)
  • Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:10, s. 2869-2877
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.
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11.
  • Fazli Yeknami, Ali, et al. (författare)
  • Low-Power DT ΔΣ Modulators Using SC Passive Filters in 65nm CMOS
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 61:2, s. 358-370
  • Tidskriftsartikel (refereegranskat)abstract
    • A comparative design study of ultra-low-power discrete-time ΔΣ modulators (ΔΣ Ms) suited for medical implant devices is presented. Aiming to reduce the analog power consumption, the objective is to investigate the effectiveness of the switched-capacitor passive Þlter. Two design variants of 2nd-order ΔΣ are analyzed and compared to a power-optimized standard active modulator ΔΣΜΑΑ. The first variant ΔΣΜΑP employs an active filer in the 1st stage and a passive filter in the less critical 2nd stage. The second variant (OTA-less ΔΣΜpp) makes use of passive Þlters in both stages. For practical verfication, all three modulators are implemented on a single chip in 65 nm CMOS technology. Designed for 500-Hz signal bandwidth, the ΔΣΜΑΑ, ΔΣΜΑP and ΔΣΜpp achieve 76 dB, 70 dB and 67 dB peak SNDR, while consuming 2.1 μW, 1.27 μW, and 0.92 μW, respectively, from a 0.9 V supply. Furthermore, the ΔΣΜpp can operate at a supply voltage reduced to 0.7 V, achieving a 65 dB SNDR at 430 nW power and 0.296 pJ/step.
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12.
  • Garrido Gálvez, Mario (författare)
  • A New Representation of FFT Algorithms Using Triangular Matrices
  • 2016
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 63:10, s. 1737-1745
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.
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13.
  • Garrido Gálvez, Mario, et al. (författare)
  • Feedforward FFT Hardware Architectures Based on Rotator Allocation
  • 2018
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 65:2, s. 581-592
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, we present new feedforward FFT hardware architectures based on rotator allocation. The rotator allocation approach consists in distributing the rotations of the FFT in such a way that the number of edges in the FFT that need rotators and the complexity of the rotators are reduced. Radix-2 and radix-2(k) feedforward architectures based on rotator allocation are presented in this paper. Experimental results show that the proposed architectures reduce the hardware cost significantly with respect to previous FFT architectures.
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14.
  • Garrido Gálvez, Mario, et al. (författare)
  • Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:7, s. 2002-2012
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents a new approach to design multiplierless constant rotators. The approach is based on a combined coefficient selection and shift-and-add implementation (CCSSI) for the design of the rotators. First, complete freedom is given to the selection of the coefficients, i.e., no constraints to the coefficients are set in advance and all the alternatives are taken into account. Second, the shift-and-add implementation uses advanced single constant multiplication (SCM) and multiple constant multiplication (MCM) techniques that lead to low-complexity multiplierless implementations. Third, the design of the rotators is done by a joint optimization of the coefficient selection and shift-and-add implementation. As a result, the CCSSI provides an extended design space that offers a larger number of alternatives with respect to previous works. Furthermore, the design space is explored in a simple and efficient way. The proposed approach has wide applications in numerous hardware scenarios. This includes rotations by single or multiple angles, rotators in single or multiple branches, and different scaling of the outputs. Experimental results for various scenarios are provided. In all of them, the proposed approach achieves significant improvements with respect to state of the art.
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15.
  • Garrido, Mario, 1981-, et al. (författare)
  • A Pipelined FFT Architecture for Real-Valued Signals
  • 2009
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 56:12, s. 2634-2643
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.
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16.
  • Garrido, Mario, 1981-, et al. (författare)
  • World’s Fastest FFT Architectures : Breaking the Barrier of 100 GS/s
  • 2019
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 66:4, s. 1507-1516
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the rotators and on selecting the most suitable FFT algorithms for these architectures. Apart from high throughput and resource efficiency, we also guarantee high accuracy in the proposed architectures. For the implementation, we have developed an automatic tool that generates the architectures as a function of the FFT size, input word length and accuracy of the rotations. We provide experimental results covering various FFT sizes, FFT algorithms, and field-programmable gate array boards. These results show that it is possible to break the barrier of 100 GS/s for FFT calculation.
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17.
  • Gustavsson, Ulf, 1975, et al. (författare)
  • An RF Carrier Bursting System using Partial Quantization Noise Cancellation
  • 2012
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 59:3, s. 515-528
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper introduces a novel method for bandpass cancellation of the quantization noise occurring in high efficiency, envelope pulsed transmitter architectures - or carrier bursting. An equivalent complex baseband model of the proposed system, including the Sigma Delta-modulator and cancellation signal generation, is developed. Analysis of the baseband model is performed, leading to analytical expressions of the power amplifier drain efficiency, assuming the use of an ideal class B power amplifier. These expressions are further used to study the impact of key system parameters, i.e. the compensation signal variance and clipping probability, on the class~B power amplifier drain efficiency and signal-to-noise ratio.The paper concludes with simulations followed by practical measurements in order to validate the functionality of the method and to evaluate the performance-trend predictions made by the theoretical framework in terms of efficiency and spectral purity.
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18.
  • Gustavsson, Ulf, 1975, et al. (författare)
  • Quantization Noise Minimization in ΣΔ-modulation based RF Transmitter Architectures
  • 2010
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 57:12, s. 3082-3091
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper we describe an optimization method for minimization of quantization noise in ΣΔ-based RF transmitters. The aim of the method is to enable the use of reconstruction filters with wider passband, or alternatively, a lower switch-rate. The method uses a general representation of the ΣΔ-converters in combination with a differentiable approximation of the quantizer. Based on this, a Monte-Carlo based algorithm is developed around the damped Gauss-Newton iteration. As a result of the suggested algorithm, the residual quantization noise after reconstruction filtering is significantly decreased. Finally, simulations using a bandlimited signal with a Gaussian distribution are used to demonstrate the capabilities of the suggested algorithm when applied with the proposed ΣΔ-modulator representation. The resulting performance is compared to several cases of traditional integrator based ΣΔ-converters, demonstrating significant improvements in terms of reduced reconstruction normalized mean square error (NMSE). This implicates that the transmitter efficiency can be improved with minor changes in the modulator implementation.
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19.
  • Hoang, Tung, 1980, et al. (författare)
  • A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit
  • 2010
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 57:12, s. 3073-3081
  • Tidskriftsartikel (refereegranskat)abstract
    • We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product generation circuitry and a reduction tree, while the second stage, thanks to a special sign-extension solution, implements all other functionality. Place-and-route evaluations using a 65-nm 1.1-V cell library show that the proposed architecture offers a 31% improvement in speed and a 32% reduction in energy per operation, averaged across operand sizes of 16, 32, 48, and 64 bits, over a reference two-cycle MAC architecture that employs a multiplier in the first stage and an accumulator in the second. When operating the proposed architecture at the lower frequency of the reference architecture the available timing slack can be used to downsize gates, resulting in a 52% reduction in energy compared to the reference. We extend the new architecture to create a versatile double-throughput MAC (DTMAC) unit that efficiently performs either multiply-accumulate or multiply operations for N-bit, 1 × N/2-bit, or 2 × N/2-bit operands. In comparison to a fixed-function 32-bit MAC unit, 16-bit multiply-accumulate operations can be executed with 67% higher energy efficiency on a 32-bit DTMAC unit. © 2006 IEEE.
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20.
  • Huan, Yuxiang, et al. (författare)
  • A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications
  • 2016
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 63:12, s. 2245-2256
  • Tidskriftsartikel (refereegranskat)abstract
    • Adapting the processor to the target application is essential in the Internet-of-Things (IoT), and thus requires customizability in order to improve energy efficiency and scalability to provide sufficient performance. In this paper, a reconfigurable and scalable control-centric architecture is proposed, and a processor consisting of two cores and an on-chip multi-mode router is implemented. Reconfigurability is enabled by a programmable sequence mapping table (SMT) which reorganizes functional units in each cycle, thus increasing hardware utilization and reducing excessive data movement for high energy efficiency. The router facilitates both wormhole and circuit switching to construct intra- or inter-chip interconnections, providing scalable performance. Fabricated in a 65-nm process, the chip exhibits 101.4 GOPS/W energy efficiency with a die size of 3.5 mm(2). The processor carries out general-purpose processing with a code size 29% smaller than the ARM Cortex M4, and improves the performance of application-specific processing by over ten times when implementing AES and RSA using SMTs instead of general-purpose C. By utilizing the on-chip router, the processor can be interconnected up to 256 nodes, with a single link bandwidth of 1.4 Gbps.
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21.
  • Huang, Boming, et al. (författare)
  • IECA : An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm(2) Area Efficiency
  • 2021
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 68:11, s. 4672-4685
  • Tidskriftsartikel (refereegranskat)abstract
    • It remains challenging for a Convolutional Neural Network (CNN) accelerator to maintain high hardware utilization and low processing latency with restricted on-chip memory. This paper presents an In-Execution Configuration Accelerator (IECA) that realizes an efficient control scheme, exploring architectural data reuse, unified in-execution controlling, and pipelined latency hiding to minimize configuration overhead out of the computation scope. The proposed IECA achieves row-wise convolution with tiny distributed buffers and reduces the size of total on-chip memory by removing 40% of redundant memory storage with shared delay chains. By exploiting a reconfigurable Sequence Mapping Table (SMT) and Finite State Machine (FSM) control, the chip realizes cycle-accurate Processing Element (PE) control, automatic loop tiling and latency hiding without extra time slots for pre-configuration. Evaluated on AlexNet and VGG-16, the IECA retains over 97.3% PE utilization and over 95.6% memory access time hiding on average. The chip is designed and fabricated in a UMC 55-nm process running at a frequency of 250 MHz and achieves an area efficiency of 30.55 GOPS/mm(2) and 0.244 GOPS/KGE (kilo-gate-equivalent), which makes an over 2.0x and 2.1x improvement, respectively, compared with that of previous related works. Implementation of the IEC control scheme uses only a 0.55% area of the 2.75 mm(2) core.
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22.
  • Ivanisevic, Nikola, et al. (författare)
  • A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
  • 2018
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 05
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.
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23.
  • Jain, Vikram, et al. (författare)
  • Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder
  • 2021
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 68:1, s. 25-34
  • Tidskriftsartikel (refereegranskat)abstract
    • Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28-nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96-10.38 dB at a post-FEC bit-error rate of 10^-15. The decoder achieves throughputs in excess of 400 Gb/s, latencies below 53 ns, and energy efficiencies of 1.14 pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5 dB, but at a significant area cost.
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24.
  • Jakobsson, Anders, et al. (författare)
  • Frequency Synthesizer With Dual Loop Frequency and Gain Calibration
  • 2013
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 60:11, s. 2911-2919
  • Tidskriftsartikel (refereegranskat)abstract
    • A 3600-MHz phase-locked loop based frequency synthesizer for UMTS applications has been developed in 0.18 $mu$ m CMOS. It incorporates a VCO frequency and loop-gain calibration technique that allows an integrated VCO frequency tuning range of 28% and a low VCO gain ($K_{rm VCO}$ of 30 MHz/V. The loop-gain calibration can compensate for not only variations in VCO gain and divider modulus, but also charge-pump current and loop filter capacitance to an accuracy of 5%. The PLL settles in 150 $mu$s including frequency and gain calibrations. No switches are used in the loop filter. The output phase noise at 1-MHz offset is ${-}123$ dBc/Hz and the integrated phase error (1 kHz–2 MHz) is 1.26 $^{circ}$.
  •  
25.
  • Jakobsson, Anders, et al. (författare)
  • Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS
  • 2015
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE Computer Society. - 1549-8328 .- 1558-0806. ; 62:3, s. 680-688
  • Tidskriftsartikel (refereegranskat)abstract
    • A method to implement quantized-state system (QSS) models in industry standard RF-IC design tools is proposed. The method is used to model a GHz-range 0.18 um CMOS phase-locked loop (PLL), and enables a truly event-driven simulation of the entire mixed-signal PLL circuit. First- and second-order (QSS and QSS2, respectively) models of the PLL loop-filter implemented in Verilog-AMS are first described in detail. These models do not rely on analog nets, and use only the event-based solver. Then, simulation results are compared to reference SPICE simulation results to prove the validity of the QSS method. The entire PLL circuit is finally simulated using the QSS model of the loop-filter, charge-pump and VCO, in conjunction with standard high-level models of the PLL digital circuits. To verify the proposed QSS method, measured phase noise is compared with simulated phase noise. It is shown that simulated phase noise accurately predicts the measured phase noise with improved accuracy, and an increase in simulation efficiency by more than 50 times. Measured and simulated results generally demonstrate the feasibility of the QSS modeling for mixed-signal circuit simulation and design.
  •  
26.
  • Jing Xu, Wei, et al. (författare)
  • Improved Filter Bank Approach for the Design of Variable Bandedge and Fractional Delay Filters
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:3, s. 764-777
  • Tidskriftsartikel (refereegranskat)abstract
    • The paper proposes an optimization technique for the design of variable digital filters with simultaneously tunable bandedge and fractional delay using a fast filter bank (FFB) approach. In the FFB approach, full band signals are split into multibands, and each band is multiplied by a proper phase shift to realize the variable fractional delay. In the proposed technique, in the formulation of the optimization of the 0th stage prototype filter of the FFB, the ripples of the filters in the subsequent stages are all taken into consideration. In addition, a shaping filter is applied to the last retained band of the FFB to form the transition band of the variable filter, such that the transition width of each band in the FFB can be relaxed to reduce the computational complexity. In total three shaping filters, constructed from a prototype filter, can be shared by different bands, so that the extra cost incurred due to the shaping filter is low.
  •  
27.
  • Johansson, Håkan, et al. (författare)
  • Add-Equalize Structures for Linear-Phase Nyquist FIR Filter Interpolators and Decimators
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:6, s. 1766-1777
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper introduces add-equalize structures for the implementation of linear-phase Nyquist (th-band) finite-length impulse response (FIR) filter interpolators and decimators. The paper also introduces a systematic design technique for these structures based on iteratively reweighted -norm minimization. In the proposed structures, the polyphase components share common parts which leads to a considerably lower implementation complexity as compared to conventional single-stage converter structures. The complexity is comparable to that of multi-stage Nyquist structures. A main advantage of the proposed structures is that they work equally well for all integer conversion factors, thus including prime numbers which cannot be handled by the regular multi-stage Nyquist converters. Moreover, the paper shows how to utilize the frequency-response masking approach to further reduce the complexity for sharp-transition specifications. It also shows how the proposed structures can be used to reduce the complexity for reconfigurable sampling rate converters. Several design examples are included to demonstrate the effectiveness of the proposed structures.
  •  
28.
  • Johansson, Håkan, et al. (författare)
  • Two Polynomial FIR Filter Structures With Variable Fractional Delay and Phase Shift
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:5, s. 1355-1365
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper introduces two polynomial finite-length impulse response (FIR) digital filter structures with simultaneously variable fractional delay (VFD) and phase shift (VPS). The structures are reconfigurable (adaptable) online without redesign and do not exhibit transients when the VFD and VPS parameters are altered. The structures can be viewed as generalizations of VFD structures in the sense that they offer a VPS in addition to the regular VFD. The overall filters are composed of a number of fixed subfilters and a few variable multipliers whose values are determined by the desired FD and PS values. A systematic design algorithm, based on iteratively reweighted l(1)- norm minimization, is proposed. It generates fixed subfilters with many zero-valued coefficients, typically located in the impulse response tails. The paper considers two different structures, referred to as the basic structure and common-subfilters structure, and compares these proposals as well as the existing cascaded VFD and VPS structures, in terms of arithmetic complexity, delay, memory cost, and transients. In general, the common-subfilters structure is superior when all of these aspects are taken into account. Further, the paper shows and exemplifies that the VFDPS filters under consideration can be used for simultaneous resampling and frequency shift of signals.
  •  
29.
  • Jung, Ylva, et al. (författare)
  • Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS
  • 2013
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 60:7, s. 1915-1928
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.
  •  
30.
  • Kanders, Hans, et al. (författare)
  • A 1 Million-Point FFT on a Single FPGA
  • 2019
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 66:10, s. 3863-3873
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, we present the first implementation of a 1 million-point fast Fourier transform (FFT) completely integrated on a single field-programmable gate array (FPGA), without the need for external memory or multiple interconnected FPGAs. The proposed architecture is a pipelined single-delay feedback (SDF) FFT. The architecture includes a specifically designed 1 million-point rotator with high accuracy and a thorough study of the word length at the different FFT stages in order to increase the signal-to-quantization-noise ratio (SQNR) and keep the area low. This also results in low power consumption.
  •  
31.
  • Karlsson, Magnus, et al. (författare)
  • Frequency Triplexer for Ultra-Wideband Systems (6–9 GHz)
  • 2013
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 60:3, s. 540-547
  • Tidskriftsartikel (refereegranskat)abstract
    • A triplexer for ultra-wideband radio implemented entirely with distributed microstrips is presented. The triplexer is composed of a triplex junction network and three bandpass filters. The circuit is integrated in a flex-rigid printed circuit board. Three flat 1 GHz sub-bands in the frequency band 6-9 GHz have been achieved. The group delay variation within each 1 GHz sub-band was measured to be less than 0.4 ns. A good agreement between simulation and measurement was obtained, e.g., less than 0.3 dB difference in the forward transmission in the majority of the frequency band.
  •  
32.
  • Khanzadi, M Reza, 1983, et al. (författare)
  • Calculation of the Performance of Communication Systems from Measured Oscillator Phase Noise
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 61:5, s. 1553-1565
  • Tidskriftsartikel (refereegranskat)abstract
    • Oscillator phase noise (PN) is one of the major problems that affect the performance of communication systems. In this paper, a direct connection between oscillator measurements, in terms of measured single-side band PN spectrum, and the optimal communication system performance, in terms of the resulting error vector magnitude (EVM) due to PN, is mathematically derived and analyzed. First, a statistical model of the PN, considering the effect of white and colored noise sources, is derived. Then, we utilize this model to derive the modified Bayesian Cramer-Rao bound on PN estimation, and use it to find an EVM bound for the system performance. Based on our analysis, it is found that the influence from different noise regions strongly depends on the communication bandwidth, i.e., the symbol rate. For high symbol rate communication systems, cumulative PN that appears near carrier is of relatively low importance compared to the white PN far from carrier. Our results also show that 1/f^3 noise is more predictable compared to 1/f^2 noise and in a fair comparison it affects the performance less.
  •  
33.
  • Kozmin, Kirill, et al. (författare)
  • Level-crossing ADC performance evaluation toward ultrasound application
  • 2009
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 56:8, s. 1708-1719
  • Tidskriftsartikel (refereegranskat)abstract
    • A performance evaluation of a level-crossing analog-to-digital converter (ADC) is presented. It is shown that its signal-to-noise ratio (SNR) does not depend on the input-signal amplitude, which results in an almost-flat SNR for amplitudes that fall into the Nyquist criteria for irregular sampling. The influence of the reconstruction procedure on SNR is discussed, and possible limitations due to the comparator and clock on the performance of the ADC are analyzed. This analysis allows for specification of comparator and clock parameters such that they do not limit the ADC performance yet are not overestimated. In conclusion, a previously known level-crossing ADC design procedure is extended.
  •  
34.
  • Liao, Z., et al. (författare)
  • FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging
  • 2022
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 69:2, s. 721-734
  • Tidskriftsartikel (refereegranskat)abstract
    • Non-line-of-sight (NLOS) imaging systems reconstruct hidden scenes using computational methods based on indirect light that diffusely reflected from relay walls. Due to the computation and memory requirements of reconstruction algorithms, real-time NLOS imaging for room-size scenes based on non-confocal data has long been challenging. This paper proposes a field programmable gate array (FPGA) accelerator for the recently proposed Rayleigh-Sommerfeld Diffraction (RSD)-based NLOS reconstruction method. In the proposed accelerator design, ring sampling and radius sampling techniques are proposed to reduce the memory requirements by reconstructing the RSD kernels with a set of kernel bases and ring sampling coefficients during the runtime. Based on that, a customized hardware architecture and the corresponding FPGA design for real-time RSD-based NLOS reconstruction is further proposed. Implementation results show that the proposed FPGA accelerator is capable of reconstructing NLOS scenes at 25 frames per second (FPS), running at a relatively slow clock frequency of 50 MHz. To the best knowledge of the authors, this is the first real-time enabled FPGA accelerator for room-size NLOS imaging with a resolution of 128×128 .
  •  
35.
  • Mohamad, Medhat, et al. (författare)
  • A Novel Transmitter Architecture for Spectrally-Precoded OFDM
  • 2018
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 65:8, s. 2592-2605
  • Tidskriftsartikel (refereegranskat)abstract
    • Frequency nulling spectral precoding is an approachthat suppresses the out-of-band emission in OFDM systems.In this paper, we discuss the transmitter architecture of thespectrally precoded OFDM systems. We design a novel precoderthat matches the practical implementation of the OFDM modulator.We show that spectral precoding can relax the analog lowpass filtering requirements of the OFDM system transmitter. Weexamine the effect of spectral precoding on the PAPR as wellas the effect of the PA on the spectral precoding suppressionperformance. We also study the compliance of the spectrallyprecoded OFDM transmitter with the 3GPP standardizationmeasures and analyze its computation complexity. At the receiverside, we analyze the in-band interference and BER performanceof the suggested precoding approach.
  •  
36.
  • Odedeyi, Temitope, et al. (författare)
  • InP DHBT Single-Stage and Multiplicative Distributed Amplifiers for Ultra-Wideband Amplification
  • 2020
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 67:11, s. 3804-3814
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper highlights the gain-bandwidth merit of the single stage distributed amplifier (SSDA) and its derivative multiplicative amplifier topologies (i.e. the cascaded SSDA (C-SSDA) and the matrix SSDA (M-SSDA)), for ultra-wideband amplification. Two new monolithic microwave integrated circuit (MMIC) amplifiers are presented: An SSDA MMIC with 7.1dB average gain and 200GHz bandwidth; and the world's first M-SSDA, which has a 12dB average gain and 170GHz bandwidth. Both amplifiers are based on an Indium Phosphide DHBT process with 250nm emitter width. To the authors best knowledge, the SSDA has the widest bandwidth for any single stage amplifier reported to date. Furthermore, the three tier M-SSDA has the highest bandwidth and gain-bandwidth product for any matrix amplifier reported to date.
  •  
37.
  • Ojani, Amin, et al. (författare)
  • Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 61:11, s. 3075-3084
  • Tidskriftsartikel (refereegranskat)abstract
    • Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the out-of-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of $-$45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.
  •  
38.
  • Ojani, Amin, et al. (författare)
  • Monte Carlo-Free Prediction of Spurious Performance for ECDLL-Based Synthesizers
  • 2015
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 62:1, s. 273-282
  • Tidskriftsartikel (refereegranskat)abstract
    • Misalignment of delay-locked loop (DLL) output edges creates an undesired periodicity, resulting in reference harmonic tones at the output spectrum of edge-combining DLL (ECDLL)-based frequency synthesizers. These spurious tones corrupt the spectral purity to an unacceptable level for wireless applications. The spur magnitude is a random variable defined by the reference frequency, number of DLL phases, harmonic order, stage-delay standard deviation (SD), duty cycle distortion (DCD) of the reference clock, and static phase error (SPE) of the locked-loop due to charge pump/phase detector imperfections. Hence, to estimate the spurious performance of such synthesizers, exhaustive Monte Carlo (MC) simulations are inevitable. Based on closed-form expressions, this paper proposes a generic predictive model for harmonic spur characterization of ECDLL-based frequency synthesizers, whose prediction accuracy is independent of synthesizer design parameters and system non-idealities. Therefore, it can replace MC method to significantly accelerate the iterative design procedure of the synthesizer, while providing comparable predictions in terms of robustness and accuracy to that of MC. Validity, accuracy, and robustness of the proposed prediction method against wide-range values of non-idealities are verified through MC simulations of both the behavioral model and transistor-level model of the synthesizer in a standard 65-nm CMOS technology.
  •  
39.
  • Onet, Raul, et al. (författare)
  • Compact Variable Gain Amplifier for a Multistandard WLAN/WiMAX/LTE Receiver
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 61:1, s. 247-257
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents a novel single-stage VGA architecture that employs two Gm cells, a voltage-controlled current attenuator, resistors and capacitors. The gain can be changed in three large steps by using digital controls, and continuously within these steps. The VGA bandwidth and output-related IP3 and 1dBCP are independent of the gain setting; the bandwidth can be programmed through a digitally-controlled capacitor array placed at its output. The proposed architecture was employed to realize the VGA for a WLAN/WiMAX/LTE radio receiver. Die area and power consumption were reduced by implementing the two Gm cells with one instantiation of a high-linearity Gm-core and scaled outputs; also, the current attenuator was implemented with a simple differential current steering circuit; finally, the load resistors were also used to sense the output common-mode level. The VGA was fabricated in 0.15 um standard CMOS process. Measurement results show the gain varying between 5 dB to 30 dB and the max bandwidth surpasses 60 MHz; 11.14 nV/root Hz input referred noise; O1dBCP of 8.6 dBm while taking 4.2 mA from a 1.8 V supply; it settles within 20 ns after a min-max step-change of the gain; it occupies 0.05 mm(2).
  •  
40.
  •  
41.
  • Pasha, Muhammad Touqir, et al. (författare)
  • A Modified All-Digital Polar PWM Transmitter
  • 2018
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-8328 .- 1558-0806. ; 65:2, s. 758-768
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.
  •  
42.
  • Rabén, Hans, et al. (författare)
  • Design of voltage multipliers for maximized DC generation in inductively coupled RFID tags
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 61:11, s. 3309-3317
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents models, circuit solutions and design procedures for maximized DC generation in inductively coupled RFID tags. An analytical model for the DC generation is derived, and relationships between the received signal in the tag coil antenna and the generated DC supply voltage using a voltage multiplier, based on both passive and active diodes, are presented. Derived from the trade-off between voltage gain in the multiplier and the tag coil at resonance, an equation for the optimum number of multiplier stages to achieve maximized DC generation is presented. Based on the derived equation, design examples are included with two typical tag coil antennas given a specification of the DC supply voltage and current. Also included in this paper is the design of a voltage multiplier based on active diodes implemented and manufactured in AMS 0.35 $mu{rm m}$ CMOS process. The active diodes are based on a concept of threshold cancellation of MOS diodes and make use of reverse leakage control to achieve full threshold cancellation.
  •  
43.
  • Rahimi, Abbas, et al. (författare)
  • High-Dimensional Computing as a Nanoscalable Paradigm
  • 2017
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 64:9, s. 2508-2521
  • Tidskriftsartikel (refereegranskat)abstract
    • We outline a model of computing with high-dimensional (HD) vectors—where the dimensionality is in the thousands. It is built on ideas from traditional (symbolic) computing and artificial neural nets/deep learning, and complements them with ideas from probability theory, statistics, and abstract algebra. Key properties of HD computing include a well-defined set of arithmetic operations on vectors, generality, scalability, robustness, fast learning, and ubiquitous parallel operation, making it possible to develop efficient algorithms for large-scale real-world tasks. We present a 2-D architecture and demonstrate its functionality with examples from text analysis, pattern recognition, and biosignal processing, while achieving high levels of classification accuracy (close to or above conventional machine-learning methods), energy efficiency, and robustness with simple algorithms that learn fast. HD computing is ideally suited for 3-D nanometer circuit technology, vastly increasing circuit density and energy efficiency, and paving a way to systems capable of advanced cognitive tasks.
  •  
44.
  • Sjöberg, Frank, et al. (författare)
  • Digital RFI Suppression in DMT-based VDSL Systems
  • 2004
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - 1549-8328 .- 1558-0806. ; 51:11, s. 2300-2312
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, we propose a method for suppressing radio frequency interference (RFI) in discrete multitone (DMT) based very high bit rate digital subscriber line (VDSL) systems. The method operates in the frequency domain of a DMT system. First, we derive a model of how an unknown narrow-band RF signal is mapped onto the DMT carriers. Then, by measuring the RFI on a few unused DMT carriers we are able to subtract RFI estimates from every modulated subcarrier. Simulation results show that this method, applied to an RFI signal with the same average power as the VDSL signal, suppresses the RFI with 40-50 dB, which reduces the average SNR loss from about 20 to less than 0.3 dB.
  •  
45.
  • Sköldberg, Jonas, 1971, et al. (författare)
  • Nanocell Devices and Architecture for Configurable Computing With Molecular Electronics
  • 2007
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 54:11, s. 2461-
  • Tidskriftsartikel (refereegranskat)abstract
    • We develop a method to configure a 3-D nonlinearnanoparticle-molecule network to performing ten out of twelvepossible combinations of two 2-bit logic gates with shared inputs.The logic gates are based on a simple circuit with adjustablelinear and fixed negative differential resistance (NDR) elements.A bistable latch for signal restoration is an integral part of thistarget circuit. The simulations show that conductive patternscan be formed by applying voltages on the input–output pinsof the nanocell. They also show that one-link gaps (short highlyresistive links) can be created within the conductive channels.Furthermore, we discuss methods for introducing NDR moleculesin these gaps, a crucial element of the target circuit. The structuresresulting from the simulations are put in an architectural context,in which complex functions can be realized from the individualnanocell logic gates.
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46.
  • Strömbeck, Frida, 1990, et al. (författare)
  • A Beyond 100-Gbps Polymer Microwave Fiber Communication Link at D-Band
  • 2023
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 70
  • Tidskriftsartikel (refereegranskat)abstract
    • A D-band (110-170 GHz) ultra high data rate link is presented and characterized. The circuits are realized in a commercial 130 nm silicon germanium (SiGe) BiCMOS process. The 3-dB bandwidth for both transmitter (Tx) and receiver (Rx) is between 125 -165 GHz, resulting in a 40 GHz bandwidth. The communication link has demonstrated transmissions up to 102 Gbps using 8-phase shift keying (PSK) modulation over a one meter long foam-cladded polymer microwave fiber (PMF) with a bit error rate (BER) of 2.1 ×10−3 . Using direct quadrature phase shift keying (QPSK), 56 Gbps was reached with a BER <10−12 . Total chip area for Tx and Rx combined, including pads, is 4.2 mm 2 .
  •  
47.
  • Strömbeck, Frida, 1990, et al. (författare)
  • Transmitter and Receiver for High Speed Polymer Microwave Fiber Communication at D-Band
  • 2022
  • Ingår i: IEEE Transactions on Circuits and Systems I: Regular Papers. - 1549-8328 .- 1558-0806. ; 69:11, s. 4674-4681
  • Tidskriftsartikel (refereegranskat)abstract
    • A chipset for high datarate polymer microwave fiber (PMF) communication is described. It consist of a PAM-4 RF-DAC and power detector (PD) and is fabricated using a commercial 130 nm SiGe BiCMOS process. A link measurement is performed over a one meter long PMF verifying that the link can support data rates up to 20 Gbps using PAM-4, with a bit error rate (BER) of < 10(-12) . The RF-DAC covers frequencies between 120-160 GHz, with a peak output power of 4 dBm. It has a stacked transistor pair as core and includes a frequency doubler at the LO input and a three stage amplifier at the output. The PD includes an amplifier and an active balun to suppress the fundamental frequency. Both circuits occupy only 1.54 mm(2) combined, including pads. The high data-rate, energy efficiency, low cost and robustness of the link makes is suitable for short range ( < 10 meters) device-to-device communication.
  •  
48.
  • Tao, Sha, et al. (författare)
  • A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems
  • 2015
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE Press. - 1549-8328 .- 1558-0806. ; 99, s. 1-10
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents an analog-to-digital converter (ADC) dedicated to neural recording systems. By using two continuous-time incremental sigma-delta ADCs in a pipeline configuration, the proposed ADC can achieve high-resolution without sacrificing the conversion rate. This two-step architecture is also power-efficient, as the resolution requirement for the incremental sigma-delta ADC in each step is significantly relaxed. To further enhance the power efficiency, a class-AB output stage and a dynamic summing comparator are used to implement the sigma-delta modulators. A prototype chip, designed and fabricated in a standard 0.18 µm CMOS process, validates the proposed ADC architecture. Measurement results show that the ADC achieves a peak signal-to-noise-plus-distortion ratio of 75.9 dB over a 4 kHz bandwidth; the power consumption is 34.8 µW, which corresponds to a figure-of-merit of 0.85 pJ/conv.
  •  
49.
  • Unnikrishnan, Vishnu, et al. (författare)
  • Mitigation of Sampling Errors in VCO-Based ADCs
  • 2017
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - New York : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 64:7, s. 1730-1739
  • Tidskriftsartikel (refereegranskat)abstract
    • Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.
  •  
50.
  • Unnikrishnan, Vishnu, et al. (författare)
  • Time-Mode Analog-to-Digital Conversion Using Standard Cells
  • 2014
  • Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 61:12, s. 3348-3357
  • Tidskriftsartikel (refereegranskat)abstract
    • Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.
  •  
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