| 1. |
- Castaneda, Oscar, et al.
(författare)
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1-bit Massive MU-MIMO Precoding in VLSI
- 2017
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3365 .- 2156-3357. ; 7:4, s. 508-522
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Tidskriftsartikel (refereegranskat)abstract
- Massive multi-user (MU) multiple-input multiple-output (MIMO) will be a core technology in fifth-generation (5G) wireless systems as it offers significant improvements in spectral efficiency compared to existing multi-antenna technologies. The presence of hundreds of antenna elements at the base station (BS), however, results in excessively high hardware costs and power consumption, and requires high interconnect throughput between the baseband-processing unit and the radio unit. Massive MU-MIMO that uses low-resolution analog-to-digital and digital-toanalog converters (DACs) has the potential to address all these issues. In this paper, we focus on downlink precoding for massive MU-MIMO systems with 1-bit DACs at the BS. The objective is to design precoders that simultaneously mitigate MU interference and quantization artifacts. We propose two nonlinear 1-bit precoding algorithms and corresponding very large-scale integration (VLSI) designs. Our algorithms rely on biconvex relaxation, which enables the design of efficient 1-bit precoding algorithms that achieve superior error-rate performance compared with that of linear precoding algorithms followed by quantization. To showcase the efficacy of our algorithms, we design VLSI architectures that enable efficient 1-bit precoding for massive MU-MIMO systems, in which hundreds of antennas serve tens of user equipments. We present corresponding field-programmable gate array (FPGA) reference implementations to demonstrate that 1-bit precoding enables reliable and high-rate downlink data transmission in practical systems.
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| 2. |
- Chen, Kun-Chih, et al.
(författare)
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A Lego-Based Neural Network Design Methodology With Flexible NoC
- 2021
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3357 .- 2156-3365. ; 11:4, s. 711-724
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Tidskriftsartikel (refereegranskat)abstract
- Deep Neural Networks (DNNs) have shown superiority in solving the problems of classification and recognition in recent years. However, DNN hardware implementation is challenging due to the high computational complexity and diverse dataflow in different DNN models. 'lb mitigate this design challenge, a large body of research has focused on accelerating specific DNN models or layers and proposed dedicated designs. However, dedicated designs for specific DNN models or layers limit the design flexibility. In this work, we take advantage of the similarity among different DNN models and propose a novel Lego-based Deep Neural Network on a Chip (DNNoC) design methodology. We work on common neural computing units (e.g., multiply-accumulation and pooling) and create some neuron computing units called NeuLego processing elements (NeuLego(PE)(s)). These NeuLego(PE)(s) are then interconnected using a flexible Network-on-Chip (NoC), allowing to construct different DNN models. To support large-scale DNN models, we enhance the reusability of each NeuLego(PE) by proposing a Lego placement method. The proposed design methodology allows leveraging different DNN model implementations, helping to reduce implementation cost and time-to-market. Compared with the conventional approaches, the proposed approach can improve the average throughput by 2,802% for given DNN models. Besides, the corresponding hardware is implemented to validate the proposed design methodology, showing on average 12,523% hardware efficiency improvement by considering the throughput and area overhead simultaneously.
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| 3. |
- Chen, Kun-Chih, et al.
(författare)
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Guest Editorial : Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators
- 2020
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2156-3357 .- 2156-3365. ; 10:3, s. 265-267
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Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to investigate the latest research about the topic of communication-aware AI subsystems and accelerators. Because of the complex communication, extensive computations, and massive storage requirements, the demand of communication-aware AI designs has been increased in recent years.
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| 4. |
- Imran, Muhammad, et al.
(författare)
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Implementation of Wireless Vision Sensor Node With a Lightweight Bi-Level Video Coding
- 2013
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : IEEE Press. - 2156-3357 .- 2156-3365. ; 3:2, s. 198-209
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Tidskriftsartikel (refereegranskat)abstract
- Wireless vision sensor networks (WVSNs) consist ofa number of wireless vision sensor nodes (VSNs) which have limitedresources i.e., energy, memory, processing, and wireless bandwidth.The processing and communication energy requirements ofindividual VSN have been a challenge because of limited energyavailability. To meet this challenge, we have proposed and implementeda programmable and energy efficient VSN architecturewhich has lower energy requirements and has a reduced designcomplexity. In the proposed system, vision tasks are partitionedbetween the hardware implemented VSN and a server. The initialdata dominated tasks are implemented on the VSN while thecontrol dominated complex tasks are processed on a server. Thisstrategy will reduce both the processing energy consumption andthe design complexity. The communication energy consumption isreduced by implementing a lightweight bi-level video coding on theVSN. The energy consumption is measured on real hardware fordifferent applications and proposed VSN is compared against publishedsystems. The results show that, depending on the application,the energy consumption can be reduced by a factor of approximately1.5 up to 376 as compared to VSN without the bi-level videocoding. The proposed VSN offers energy efficient, generic architecturewith smaller design complexity on hardware reconfigurableplatform and offers easy adaptation for a number of applicationsas compared to published systems.
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| 5. |
- Johansson, Håkan
(författare)
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On FIR Filter Approximation of Fractional-Order Differentiators and Integrators
- 2013
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3357 .- 2156-3365. ; 3:3, s. 404-415
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Tidskriftsartikel (refereegranskat)abstract
- This paper considers finite-length impulse response (FIR) filter approximation of differentiators and integrators, collectively called differintegrators. The paper introduces and compares three different FIR filter structures for this purpose, all of which are optimized in the minimax sense using iterative reweighted l(1)-norm minimization. One of the structures is the direct-form structure, but featuring equal-valued taps and zero-valued taps, the latter corresponding to sparse filters. The other two structures comprise two subfilters in parallel and cascade, respectively. In their basic forms, nothing is gained by realizing the filters in parallel or in cascade, instead of directly. However, as the paper will show, these forms enable substantial further complexity reductions, because they comprise symmetric and antisymmetric subfilters of different orders, and also features additional equal-valued and zero-valued taps. The cascade structure employs a structurally sparse filter. The additional sparsity, as well as tap equalities, are for all three structures found automatically in the design via the l(1)-norm minimization. Design examples included reveal feasible multiplication complexity savings of more than 50% in comparison with regular (unconstrained) direct-form structures. In addition, an example shows that the proposed designs can even have lower complexity than existing infinite-length impulse response filter designs.
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| 6. |
- Keshmiri, Vahid, et al.
(författare)
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A Silicon-Organic Hybrid Voltage Equalizer for Supercapacitor Balancing
- 2017
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2156-3357 .- 2156-3365. ; 7:1, s. 114-122
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Tidskriftsartikel (refereegranskat)abstract
- Cell voltage equalizers are an important part in electric energy storage systems comprising series-connected cells, for example, supercapacitors. Hybrid electronics with silicon chips and printed devices enables electronic systems with moderate performance and low cost. This paper presents a silicon-organic hybrid voltage equalizer to balance and protect series-connected supercapacitor cells during charging. Printed organic electrochemical transistors with conducting polymer poly(3,4-ethylenedioxythiophene): poly(styrene sulfonate) (PEDOT:PSS) are utilized to bypass excess current when the supercapacitor cells are fully charged to desired voltages. In this study, low-cost silicon microcontrollers (ATtiny85) are programmed to sense voltages across the supercapacitor cells and control the organic electrochemical transistors to bypass charging current when the voltages exceed 1 V. Experimental results show that the hybrid equalizer with the organic electrochemical transistors works in dual-mode, switched-transistor mode or constant-resistor mode, depending on the charging current applied (0.3-100 mA). With the voltage equalizer, capacitors are charged equally regardless of their capacitances. This work demonstrates a low-cost hybrid solution for supercapacitor balancing modules at large-scale packs.
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| 7. |
- Nabavinejad, Seyed M., et al.
(författare)
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An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators
- 2020
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers Inc.. - 2156-3357 .- 2156-3365. ; 10:3, s. 268-282
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Tidskriftsartikel (refereegranskat)abstract
- Deep Neural Networks (DNNs) have shown significant advantages in many domains, such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations. However, due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the huge communication overheads and storage requirements. As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study. Currently, a large body of research aims to find an efficient on-chip interconnection to achieve low-power and high-bandwidth DNN computing. This paper provides a comprehensive investigation of the recent advances in efficient on-chip interconnection and design methodology of the DNN accelerator design. First, we provide an overview of the different interconnection methods on the DNN accelerator. Then, the interconnection methods on the non-ASIC DNN accelerator will be discussed. On the other hand, with the flexible interconnection, the DNN accelerator can support different computing flow, which increases the computing flexibility. With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper. Finally, we investigate the emerging interconnection technologies (e.g., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs. With this article, the readers are able to: 1) understand the interconnection design for DNN accelerators; 2) evaluate DNNs with different on-chip interconnection; 3) familiarize with the trade-offs under different interconnections.
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| 8. |
- Nilsson, Emil, et al.
(författare)
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Power Consumption of Integrated Low-Power Receivers
- 2014
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - Piscataway, N.J. : IEEE Press. - 2156-3357 .- 2156-3365. ; 4:3, s. 273-283
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Tidskriftsartikel (refereegranskat)abstract
- With the advent of Internet of Things (IoT) it has become clear that radio-frequency (RF) designers have to be aware of power constraints, e.g., in the design of simplistic ultra-low power receivers often used as wake-up radios (WuRs). The objective of this work, one of the first systematic studies of power bounds for RF-systems, is to provide an overview and intuitive feel for how power consumption and sensitivity relates for low-power receivers. This was done by setting up basic circuit schematics for different radio receiver architectures to find analytical expressions for their output signal-to-noise ratio including power consumption, bandwidth, sensitivity, and carrier frequency. The analytical expressions and optimizations of the circuits give us relations between dc-energy-per-bit and receiver sensitivity, which can be compared to recent published low-power receivers. The parameter set used in the analysis is meant to reflect typical values for an integrated 90 nm complementary metal-oxide-semiconductor fabrication processes, and typical small sized RF lumped components.
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| 9. |
- Nilsson, Emil, et al.
(författare)
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Ultra Low Power Wake-Up Radio Using Envelope Detector and Transmission Line Voltage Transformer
- 2013
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3357 .- 2156-3365. ; 3:1, s. 5-12
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Tidskriftsartikel (refereegranskat)abstract
- An ultra-low power wake-up radio receiver using no oscillators is described. The radio utilizes an envelope detector followed by a baseband amplifier and is fabricated in a 130-nm complementary metal-oxide-semiconductor process. The receiver is preceded by a passive radio-frequency voltage transformer, also providing 50 Omega antenna matching, fabricated as transmission lines on the FR4 chip carrier. A sensitivity of -47 dBm with 200 kb/s on-off keying modulation is measured at a current consumption of 2.3 mu A from a 1 V supply. No trimming is used. The receiver accepts a dBm continuous wave blocking signal, or modulated blockers 6 dB below the sensitivity limit, with no loss of sensitivity.
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| 10. |
- Sanchez Perez, Cesar, 1981, et al.
(författare)
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Design and applications of a 300-800 MHz tunable matching network
- 2013
-
Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3365 .- 2156-3357. ; 3:4, s. 531-540
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, the optimized design, characterization and applications of a broadband 300-800 MHz ($\sim$ 91% fractional bandwidth) digitally-controlled tunable matching network is presented. The design employs PIN diodes as switching components and a repetitive structure of basic cells using lumped reactive elements. After an intensive and complex optimization process, a Smith chart coverage (return losses better than 10 dB and losses lower than 2 dB) above 60% is obtained in all the bandwidth reaching 75% in the middle of the band (400-700 MHz). The potential of the manufactured tunable matching network for antenna mismatch compensation, antenna bandwidth extension and power amplifier efficiency improvement in back-off is showed. © 2011 IEEE.
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| 11. |
- Xie, Li, et al.
(författare)
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Heterogeneous integration of bio-sensing system-on-chip and printed electronics
- 2012
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3357 .- 2156-3365. ; 2:4, s. 672-682
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a heterogeneous integration platform for bio-sensing applications, which seamlessly integrates low-power silicon-based circuits with cost-effective printed electronics. A prototype of wearable Bio-Sensing Node is fabricated to investigate the suitability of this integration approach. A customized mixed-signal system-on-chip (SoC) with the size of 1.5× 3.0 mm2 is utilized to amplify, digitize, buffer, and transmit the sensed bio-signals. Inkjet printing technology is employed to print nano-particle silver ink on a flexible substrate to fabricate chip-on-flex, electrodes as well as interconnections. This additive and digital fabrication technology enables fast prototype of the customized electrode pattern. Its high accuracy and fine resolution features allow the direct integration of the bare die (the pad size of 65 μ m and pitch size of 90 μ m) on the flexible substrate, which significantly miniaturizes the wearable system. The optimal size and layout of printed electrodes are investigated through the in vivo test for electrocardiogram recording applications. The total size of the implemented Bio-Sensing Node is 4.5× 2.5 cm2, which is comparable with a commercial electrode. This inkjet printed heterogeneous integration approach offers a promising solution for the next-generation cost-effective personalized wearable healthcare monitoring devices.
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| 12. |
- Yao, Yuan, 1986-
(författare)
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Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core Processors
- 2023
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3357 .- 2156-3365. ; 13:1, s. 58-72
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Tidskriftsartikel (refereegranskat)abstract
- We propose a novel technique which exploits the concept of Game-of-Life (GoL) originated from cellular automata to achieve a light-weight yet effective temperature-aware DVFS for tile-based Chip Many-Core Processors (CMPs). The proposed DVFS mechanism is based on the strategy that a CMP V/F region, consisting of several tiles sharing the same V/F level, first determines the local V/F level according to core and uncore performance interests of the resident tiles. Then, based on the temperatures of both local and neighbor V/F regions, the performance based V/F policy is revised towards thermal safety, minimizing the occurrence of chip thermal urgency threshold (TUT) violation. As such, our temperature-aware DVFS strategy implements an ecosystem where V/F regions try to secure as much performance as possible, but a sustainable thermal environment for itself and neighbor regions is also maintained, essentially mimicking the behavior of living cells that co-exist harmonically in a common environment. Full-system evaluations with PARSEC and SPEC OMP2012 multi-threaded benchmarks show that our GoL based temperature-aware DVFS technique can averagely reduce TUT violation by 43.4% (59.5% in maximum) compared to a thermal-oblivious DVFS mechanism and by 20.7% (31.9% in maximum) compared to a local-temperature aware DVFS mechanism, with graceful performance degradation.
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| 13. |
- Yao, Yuan, 1986-
(författare)
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SE-CNN : Convolution Neural Network Acceleration via Symbolic Value Prediction
- 2023
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3357 .- 2156-3365. ; 13:1, s. 73-85
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Tidskriftsartikel (refereegranskat)abstract
- CNNs are difficult to achieve inter-layer parallelism because of the data dependence between layers. In the paper, we propose Symbolic-Execution CNN (SE-CNN), which breaks data dependence between CNN layers via value prediction. Our insight is that in post-trained CNNs, only a subset (less than 10%) of neurons are activated (producing non-zero values) to identify patterns in inputs while most of the other neurons remain silent (producing zeros). This is because given an input image there are only a limited number of features presented. Thus, within the CNN, the neurons that are sensitive to the given features are more exercised than the others. Based on this insight, SE-CNN works in two successive phases: A parallel computation phase and a serial correction phase. In the parallel computation phase, each CNN layer starts computation simultaneously based on predicted inputs: we predict most of the neurons having zeros as inputs. For non-zero input neurons we predict their inputs for the next input image the same as the previous ones. In the serial correction phase, each layer compares the predicted inputs with the real ones to correct its computation results if necessary. If a neuron has predicted correctly its input during the parallel phase, thus the corresponding neuron passes its serial phase. Otherwise the neuron will amend its prediction with a light-weight result amendment mechanism based on the real inputs. We imple-ment SE-CNN on top of the streaming processor of a state-of-the-art general purpose GPU (GPGPU) architecture, adding marginal hardware overheads in area and power consumption. We also provide application programming interfaces (APIs) so that CNNs that have already been implemented can directly enjoy the benefits of our technique. We utilize GPGPU-sim as our experimental platform, benchmarked with 9 well-accepted CNNs from recent years' ILSVRC contests. Experimental results show that compared to other three state-of-the-art GPU based CNN acceleration mechanisms, SE-CNN can averagely achieve 13.4x, 10.4x and 7.9x (maximally 22.0x, 18.7x and 16.4x) CNN execution speedup while maintaining over 95% of classification accuracy.
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| 14. |
- Yun, Yixiao, 1987, et al.
(författare)
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Multi-View ML Object Tracking with Online Learning on Riemannian Manifolds by Combining Geometric Constraints
- 2013
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3365 .- 2156-3357. ; 3:2, s. 12 -197
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Tidskriftsartikel (refereegranskat)abstract
- This paper addresses issues in object tracking with occlusion scenarios, where multiple uncalibrated cameras with overlapping fields of view are exploited. We propose a novel method where tracking is first done independently in each individual view and then tracking results are mapped from different views to improve the tracking jointly. The proposed tracker uses the assumptions that objects are visible in at least one view and move uprightly on a common planar ground that may induce a homography relation between views. A method for online learning of object appearances on Riemannian manifolds is also introduced. The main novelties of the paper include: (a) define a similarity measure, based on geodesics between a candidate object and a set of mapped references from multiple views on a Riemannian manifold; (b) propose multiview maximum likelihood (ML) estimation of object bounding box parameters, based on Gaussian-distributed geodesics on the manifold; (c) introduce online learning of object appearances on the manifold, taking into account of possible occlusions; (d) utilize projective transformations for objects between views, where parameters are estimated from warped vertical axis by combining planar homography, epipolar geometry and vertical vanishing point; (e) embed single-view trackers in a three-layer multi-view tracking scheme. Experiments have been conducted on videos from multiple uncalibrated cameras, where objects containlong-term partial/full occlusions, or frequent intersections. Comparisons have been made with three existing methods, where the performance is evaluated both qualitatively and quantitatively. Results have shown the effectiveness of the proposed method in terms of robustness against tracking drift caused by occlusions.
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| 15. |
- Bryant, Carl, et al.
(författare)
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A 0.55mW SAW-Less Receiver Front-End for Bluetooth Low Energy Applications
- 2014
-
Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3365. ; 4:3, s. 262-272
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Tidskriftsartikel (refereegranskat)abstract
- Email Print Request Permissions Save to Project This paper presents an ultra-low power direct conversion receiver front-end operating at 2.6 GHz with high out-of-band linearity and low quadrature error. This is achieved through the use of efficient mixers with improved out-of-band suppression, including rejection of the second harmonic, and an local-oscillator generator achieving current reuse and rejection of voltage-controlled oscillator signal imbalance through the use of complementary devices. Manufactured in 65 nm complementary metal-oxide-semiconductor and with a power consumption below 550 μW from a 0.85 V supply, the front-end achieves a conversion gain of 41 dB and a noise figure of 9.6 dB. It has an out-of-band IIP3 and IIP2 of -3 dBm and 29.5 dBm, respectively. The quadrature phase error is below 0.6°. Requiring only two inductors it occupies an area of just 0.15 mm2 excluding pads.
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| 16. |
- Meinerzhagen, Pascal, et al.
(författare)
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Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
- 2011
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Ingår i: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. - 2156-3365. ; 1:2, s. 173-182
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed, routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.
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| 17. |
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