| 1. |
- Diaz, Isael, et al.
(författare)
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Selective Channelization on an SDR Platform for LTE-A Carrier Aggregation.
- 2012
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Ingår i: 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012. - 9781467312615 ; , s. 316-319
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Konferensbidrag (refereegranskat)abstract
- The total transmission bandwidth and component carrier aggregation proposed by LTE-Advanced, sets a new challenge to the design of terminals. This article presents a way to assure terminals cope with the large bandwidth in an efficient manner. Various filtering methods are explored showing that an SDR architecture, such as ADRES (Architecture for Dynamically Reconfigurable Embedded Systems), is suitable for dynamic adaptation of filtering methods as function of the aggregation scheme and the individual bandwidth assigned to each terminal. This method is able to reduce the processing load by 70% for LTE-A with legacy support and possibly higher reduction when LTE legacy is not supported. Simulations conclude that the performance loss derived from the proposed method is marginal with no negative repercussion on the posterior baseband stages.
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| 2. |
- Sherazi, Syed Muhammad Yasser, et al.
(författare)
-
A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
- 2012
-
Ingår i: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012). - 9781467312615 - 9781467312615
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Konferensbidrag (refereegranskat)abstract
- Measurements of a sub-threshold (sub-VT) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-VT domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavors are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.
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| 3. |
- Tao, Sha, et al.
(författare)
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Analysis of Exponentially Decaying Pulse Shape DACs in Continuous-Time Sigma-Delta Modulators
- 2012
-
Ingår i: Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on. - : IEEE. - 9781467312615 ; , s. 424-427
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Konferensbidrag (refereegranskat)abstract
- The performance of continuous-time (CT) sigma-delta (ΣΔ) modulators is severely degraded by the clock jitter induced timing variation in their feedback digital-to-analog converters (DACs). To mitigate this non-ideality, jitter sensitivity reduction techniques that employ exponentially decaying pulse shape DACs have been recently reported. In this paper, exponentially decaying DACs are investigated and generalized expressions are derived. In addition, another exponentially decaying DAC proposed, which can potentially achieve both good jitter immunity and amplitude efficiency. To validate the theoretical results, the proposed DAC, together with other exponentially decaying DACs, are employed in a 3rd order 1-bit CT ΣΔ modulator test case and evaluated through behavioral simulations.
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