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- Alam, Ashraful, et al.
(författare)
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Parallelization of the Estimation Algorithm of the 3D Structure Tensor
- 2012
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Ingår i: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012. - Piscataway, N.J. : IEEE Press. - 9781467329194 - 9781467329217
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Konferensbidrag (refereegranskat)abstract
- The three dimensional structure tensor algorithm (3D-STA) is often used in image processing applications to compute the optical flow or to detect local 3D structures and their directions. This algorithm is computationally expensive due to many computations that are required to calculate the gradient, the tensor, and to smooth every pixel of the image frames. Therefore, it is important to parallelize the implementation to achieve high performance. In this paper we present two parallel implementations of 3D-STA; namely moderately parallelized and highly parallelized implementation, on a massively parallel reconfigurable array. Finally, we evaluate the performance of the generated code and results are compared with another optical flow implementation. The throughput achieved by the moderately parallelized implementation is approximately half of the throughput of the Optical flow implementation, whereas the highly parallelized implementation results in a 2x gain in throughput as compared to the optical flow implementation. © 2012 IEEE.
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| 2. |
- Lifa, Adrian Alin, et al.
(författare)
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Minimization of Average Execution Time Based on Speculative FPGA Configuration Prefetch
- 2012
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Ingår i: International Conference on ReConFigurable Computing and FPGAs, 2012. - : IEEE. - 9781467329194
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Konferensbidrag (refereegranskat)abstract
- One of the main drawbacks that significantly impacts the performance of dynamically reconfigurable systems (like FPGAs), is their high reconfiguration overhead. Configuration prefetching is one method to reduce this penalty by overlapping FPGA reconfigurations with useful computations. In this paper we propose a speculative approach that schedules prefetches at design time and simultaneously performs HW/SW partitioning, in order to minimize the expected execution time of an application. Our method prefetches and executes in hardware those configurations that provide the highest performance improvement. The algorithm takes into consideration profiling information (such as branch probabilities and execution time distributions), correlated with the application characteristics. Compared to the previous state-of-art, we reduce the reconfiguration penalty with 34% on average, and with up to 59% for particular case studies.
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