SwePub - sökning: WFRF:(Daneshtalab Masoud)

Numrering	Referens	Omslagsbild	Hitta
1.	Afsharmazayejani, R., et al. (författare) HoneyWiN : Novel honeycomb-based wireless NoC architecture in many-core era 2018 Ingår i: Lecture Notes in Computer Science. - Cham : Springer Verlag. - 0302-9743 .- 1611-3349. ; 10824 LNCS, s. 304-316 Tidskriftsartikel (refereegranskat)abstract Although NoC-based systems with many cores are commercially available, their multi-hop nature has become a bottleneck on scaling performance and energy consumption parameters. Alternatively, hybrid wireless NoC provides a postern by exploiting single-hop express links for long-distance communications. Also, there is a common wisdom that grid-like mesh is the most stable topology in conventional designs. That is why almost all of the emerging architectures had been relying on this topology as well. In this paper, first we challenge the efficiency of the grid-like mesh in emerging systems. Then, we propose HoneyWiN, a hybrid reconfigurable wireless NoC architecture that relies on the honeycomb topology. The simulation results show that on average HoneyWiN saves 17% of energy consumption while increases the network throughput by 10% compared to its wireless mesh counterpart.
2.	Ahmadilivani, M. H., et al. (författare) A Systematic Literature Review on Hardware Reliability Assessment Methods for Deep Neural Networks 2024 Ingår i: ACM Computing Surveys. - : ASSOC COMPUTING MACHINERY. - 0360-0300 .- 1557-7341. ; 56:6 Tidskriftsartikel (refereegranskat)abstract Artificial Intelligence (AI) and, in particular, Machine Learning (ML), have emerged to be utilized in various applications due to their capability to learn how to solve complex problems. Over the past decade, rapid advances in ML have presented Deep Neural Networks (DNNs) consisting of a large number of neurons and layers. DNN Hardware Accelerators (DHAs) are leveraged to deploy DNNs in the target applications. Safety-critical applications, where hardware faults/errors would result in catastrophic consequences, also benefit from DHAs. Therefore, the reliability of DNNs is an essential subject of research. In recent years, several studies have been published accordingly to assess the reliability of DNNs. In this regard, various reliability assessment methods have been proposed on a variety of platforms and applications. Hence, there is a need to summarize the state-of-the-art to identify the gaps in the study of the reliability of DNNs. In this work, we conduct a Systematic Literature Review (SLR) on the reliability assessment methods of DNNs to collect relevant research works as much as possible, present a categorization of them, and address the open challenges. Through this SLR, three kinds of methods for reliability assessment of DNNs are identified, including Fault Injection (FI), Analytical, and Hybrid methods. Since the majority of works assess the DNN reliability by FI, we characterize different approaches and platforms of the FI method comprehensively. Moreover, Analytical and Hybrid methods are propounded. Thus, different reliability assessment methods for DNNs have been elaborated on their conducted DNN platforms and reliability evaluation metrics. Finally, we highlight the advantages and disadvantages of the identified methods and address the open challenges in the research area. We have concluded that Analytical and Hybrid methods are light-weight yet sufficiently accurate and have the potential to be extended in future research and to be utilized in establishing novel DNN reliability assessment frameworks.
3.	Ahmadilivani, M. H., et al. (författare) Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks 2023 Ingår i: Proc. IEEE Int. Symp. Defect Fault Toler. VLSI Nanotechnol. Syst., DFT. - : Institute of Electrical and Electronics Engineers Inc.. - 9798350315004 Konferensbidrag (refereegranskat)abstract The reliability of Artificial Neural Networks (ANNs) has emerged as a prominent research topic due to their increasing utilization in safety-critical applications. Long Short-Term Memory (LSTM) ANNs have demonstrated significant advantages in healthcare applications, primarily attributed to their robust processing of time-series data and memory-facilitated capabilities. This paper, for the first time, presents a comprehensive and fine-grain analysis of the resilience of LSTM-based ANNs in the context of gait analysis using fault injection into weights. Additionally, we improve their resilience by replacing faulty weights with zero, enabling ANNs to withstand environments that are up to 20 times harsher while experiencing up to 7 times fewer critical faults than an unprotected ANN.
4.	Ahmadilivani, Mohammad Hasan, et al. (författare) DeepVigor : VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment 2023 Ingår i: 2023 IEEE EUROPEAN TEST SYMPOSIUM, ETS. - : IEEE. - 9798350336344 Konferensbidrag (refereegranskat)abstract Deep Neural Networks (DNNs) and their accelerators are being deployed ever more frequently in safety-critical applications leading to increasing reliability concerns. A traditional and accurate method for assessing DNNs' reliability has been resorting to fault injection, which, however, suffers from prohibitive time complexity. While analytical and hybrid fault injection-/analyticalbased methods have been proposed, they are either inaccurate or specific to particular accelerator architectures. In this work, we propose a novel accurate, fine-grain, metric-oriented, and accelerator-agnostic method called DeepVigor that provides vulnerability value ranges for DNN neurons' outputs. An outcome of DeepVigor is an analytical model representing vulnerable and non-vulnerable ranges for each neuron that can be exploited to develop different techniques for improving DNNs' reliability. Moreover, DeepVigor provides reliability assessment metrics based on vulnerability factors for bits, neurons, and layers using the vulnerability ranges. The proposed method is not only faster than fault injection but also provides extensive and accurate information about the reliability of DNNs, independent from the accelerator. The experimental evaluations in the paper indicate that the proposed vulnerability ranges are 99.9% to 100% accurate even when evaluated on previously unseen test data. Also, it is shown that the obtained vulnerability factors represent the criticality of bits, neurons, and layers proficiently. DeepVigor is implemented in the PyTorch framework and validated on complex DNN benchmarks.
5.	Ahmadilivani, M. H., et al. (författare) Enhancing Fault Resilience of QNNs by Selective Neuron Splitting 2023 Ingår i: AICAS 2023 - IEEE International Conference on Artificial Intelligence Circuits and Systems, Proceeding. - : Institute of Electrical and Electronics Engineers Inc.. - 9798350332674 Konferensbidrag (refereegranskat)abstract The superior performance of Deep Neural Networks (DNNs) has led to their application in various aspects of human life. Safety-critical applications are no exception and impose rigorous reliability requirements on DNNs. Quantized Neural Networks (QNNs) have emerged to tackle the complexity of DNN accelerators, however, they are more prone to reliability issues.In this paper, a recent analytical resilience assessment method is adapted for QNNs to identify critical neurons based on a Neuron Vulnerability Factor (NVF). Thereafter, a novel method for splitting the critical neurons is proposed that enables the design of a Lightweight Correction Unit (LCU) in the accelerator without redesigning its computational part.The method is validated by experiments on different QNNs and datasets. The results demonstrate that the proposed method for correcting the faults has a twice smaller overhead than a selective Triple Modular Redundancy (TMR) while achieving a similar level of fault resiliency.
6.	Ahmadilivani, Mohammed. H., et al. (författare) Special Session : Approximation and Fault Resiliency of DNN Accelerators 2023 Ingår i: Proceedings of the IEEE VLSI Test Symposium. - : IEEE Computer Society. - 9798350346305 Konferensbidrag (refereegranskat)abstract Deep Learning, and in particular, Deep Neural Network (DNN) is nowadays widely used in many scenarios, including safety-critical applications such as autonomous driving. In this context, besides energy efficiency and performance, reliability plays a crucial role since a system failure can jeopardize human life. As with any other device, the reliability of hardware architectures running DNNs has to be evaluated, usually through costly fault injection campaigns. This paper explores approximation and fault resiliency of DNN accelerators. We propose to use approximate (AxC) arithmetic circuits to agilely emulate errors in hardware without performing fault injection on the DNN. To allow fast evaluation of AxC DNN, we developed an efficient GPU-based simulation framework. Further, we propose a fine-grain analysis of fault resiliency by examining fault propagation and masking in networks.
7.	Akbari, N., et al. (författare) A Customized Processing-in-Memory Architecture for Biological Sequence Alignment 2018 Ingår i: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors. - : Institute of Electrical and Electronics Engineers Inc.. - 9781538674796 Konferensbidrag (refereegranskat)abstract Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. The design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.
8.	Aldinucci, Marco, et al. (författare) Preface 2017 Ingår i: The international journal of high performance computing applications. - : Sage Publications. - 1094-3420 .- 1741-2846. ; 31:3, s. 179-180 Tidskriftsartikel (refereegranskat)
9.	Amin, Yoosefi, et al. (författare) Efficient On-device Transfer Learning using Activation Memory Reduction 2023 Ingår i: Int. Conf. Fog Mob. Edge Comput., FMEC. - : Institute of Electrical and Electronics Engineers Inc.. - 9798350316971 ; , s. 210-215 Konferensbidrag (refereegranskat)abstract On-device transfer learning suggests fine-tuning pretrained neural networks on new input data directly on edge devices. The memory limitation of edge devices necessitates using memory-efficient fine-tuning methods. Fine-tuning involves two primary phases: the forward-pass phase and the backwardpass phase. The forward-pass phase generates output activations, and the backward-pass phase computes gradients and updates the parameters accordingly. Although the forward-pass phase demands a temporary memory to store a layer’s input and output activations, the backward-pass phase may require storing the output activations from all layers to compute gradients. This fact introduces the memory cost of the backward-pass phase as the main contributor to the huge training memory demands of deep neural networks (DNNs), which has been the focus of many studies. However, little attention has been made to how the temporary activation memory involved in the forward-pass phase may also act as the memory bottleneck, which is the main focus of this paper. This paper aims to mitigate this memory bottleneck by pruning unimportant channels from layers that require significant temporary activation memory. Experimental results demonstrate how the proposed method effectively reduces peak activation memory and total memory costs of MobileNetV2 by 65% and 59%, respectively, at the cost of 3% accuracy drop.
10.	Anwar, Hassan, et al. (författare) Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures 2014 Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : ACM. - 9781450328227 ; , s. 64-67 Konferensbidrag (refereegranskat)abstract Today, reconfigurable architectures are becoming increas- ingly popular as the candidate platforms for neural net- works. Existing works, that map neural networks on re- configurable architectures, only address either FPGAs or Networks-on-chip, without any reference to the Coarse-Grain Reconfigurable Architectures (CGRAs). In this paper we investigate the overheads imposed by implementing spiking neural networks on a Coarse Grained Reconfigurable Ar- chitecture (CGRAs). Experimental results (using point to point connectivity) reveal that up to 1000 neurons can be connected, with an average response time of 4.4 msec.
11.	Asadi, M., et al. (författare) Accurate detection of paroxysmal atrial fibrillation with certified-GAN and neural architecture search 2023 Ingår i: Scientific Reports. - : NLM (Medline). - 2045-2322. ; 13:1 Tidskriftsartikel (refereegranskat)abstract This paper presents a novel machine learning framework for detecting PxAF, a pathological characteristic of electrocardiogram (ECG) that can lead to fatal conditions such as heart attack. To enhance the learning process, the framework involves a generative adversarial network (GAN) along with a neural architecture search (NAS) in the data preparation and classifier optimization phases. The GAN is innovatively invoked to overcome the class imbalance of the training data by producing the synthetic ECG for PxAF class in a certified manner. The effect of the certified GAN is statistically validated. Instead of using a general-purpose classifier, the NAS automatically designs a highly accurate convolutional neural network architecture customized for the PxAF classification task. Experimental results show that the accuracy of the proposed framework exhibits a high value of 99.0% which not only enhances state-of-the-art by up to 5.1%, but also improves the classification performance of the two widely-accepted baseline methods, ResNet-18, and Auto-Sklearn, by [Formula: see text] and [Formula: see text].
12.	Asghari, S. A., et al. (författare) A software implemented comprehensive soft error detection method for embedded systems 2020 Ingår i: Microprocessors and microsystems. - : Elsevier. - 0141-9331 .- 1872-9436. ; 77 Tidskriftsartikel (refereegranskat)abstract This paper presents a comprehensive software-based technique that is capable of detecting soft errors in embedded systems. Soft errors can be categorized into Control Flow Errors (CFEs) and data errors. The CFEs change the flow of the program erroneously and data errors also change the results. In this paper, a new comprehensive method is presented to detect both (based on combination of authors’ previous works). In order to evaluate the proposed method, a new factor is defined that considers three main parameters simultaneously; namely fault coverage, memory overhead, and performance overhead. Since these parameters are very important in safety critical applications, they should be improved concurrently. The experimental results on SPEC2000 benchmarks show that the Evaluation Factor of the proposed method is 50% better than the Relationship Signatures for Control Flow Checking with Data Validation (RSCFCDV) methods, which are suggested in the literature.
13.	Ashjaei, Mohammad, 1980-, et al. (författare) Towards a Predictable and Cognitive Edge-Cloud Architecture for Industrial Systems 2022 Ingår i: Proceedings of RAGE 2022. Konferensbidrag (refereegranskat)
14.	Ashjaei, Seyed Mohammad Hossein, 1980-, et al. (författare) Time-Sensitive Networking in automotive embedded systems : State of the art and research opportunities 2021 Ingår i: Journal of systems architecture. - : Elsevier B.V.. - 1383-7621 .- 1873-6165. ; 117 Tidskriftsartikel (refereegranskat)abstract The functionality advancements and novel customer features that are currently found in modern automotive systems require high-bandwidth and low-latency in-vehicle communications, which become even more compelling for autonomous vehicles. In a recent effort to meet these requirements, the IEEE Time-Sensitive Networking (TSN) task group has developed a set of standards that introduce novel features in Switched Ethernet. TSN standards offer, for example, a common notion of time through accurate and reliable clock synchronization, delay bounds for real-time traffic, time-driven transmissions, improved reliability, and much more. In order to fully utilize the potential of these novel protocols in the automotive domain, TSN should be seamlessly integrated into the state-of-the-art and state-of-practice model-based development processes for automotive embedded systems. Some of the core phases in these processes include software architecture modeling, timing predictability verification, simulation, and hardware realization and deployment. Moreover, throughout the development of automotive embedded systems, the safety and security requirements specified on these systems need to be duly taken into account. In this context, this work provides an overview of TSN in automotive applications and discusses the recent technological developments relevant to the adoption of TSN in automotive embedded systems. The work also points at the open challenges and future research directions.
15.	Bakhouya, Mohamed, et al. (författare) Many-core System-on-Chip : architectures and applications 2016 Ingår i: Microprocessors and microsystems. - : Elsevier. - 0141-9331 .- 1872-9436. ; 43, s. 1-3 Tidskriftsartikel (refereegranskat)
16.	Baloch, Naveed Khan, et al. (författare) Defender : A Low Overhead and Efficient Fault-Tolerant Mechanism for Reliable on-Chip Router 2019 Ingår i: IEEE Access. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2169-3536. ; 7, s. 142843-142854 Tidskriftsartikel (refereegranskat)abstract The ever-shrinking size of a transistor has made Network on Chip (NoC) susceptible to faults. A single error in the NoC can disrupt the entire communication. In this paper, we introduce Defender, a fault-tolerant router architecture, that is capable of tolerating permanent faults in all the parts of the router. We intend to employ structural modifications in baseline router design to achieve fault tolerance. In Defender we provide the fault tolerance to the input ports and routing computation unit by grouping the neighboring ports together. Default winner strategy is used to provide fault resilience to the virtual channel arbiters and switch allocators. Multiple routes are provided to the crossbar to tolerate the faults. Defender provides improved fault tolerance to all stages of routers as compared to the currently prevailing fault tolerant router architectures. Reliability analysis using silicon protection factor (SPF) and Mean Time to Failure (MTTF) metrics confirms that our proposed design Defender is 10.78 times more reliable than baseline unprotected router and then the current state of the art architectures.
17.	Berisa, Aldin, et al. (författare) AVB-aware Routing and Scheduling for Critical Traffic in Time-sensitive Networks with Preemption 2022 Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : Association for Computing Machinery. - 9781450396509 ; , s. 207-218 Konferensbidrag (refereegranskat)abstract The Time-Sensitive Network (TSN) amendments and protocols add capabilities on top of standard 802.1 Ethernet for guaranteeing the timeliness of both (isochronous) scheduled traffic (ST) and shaped (audio-video) communication (AVB) in distributed applications. ST streams are guaranteed via an offline computed schedule controlling the time-aware gate mechanism of IEEE 802.1Qbv, while AVB real-time streams are shaped via a credit-based shaper (CBS) and scheduler with lower-priority than ST. Although the two traffic classes use different TSN mechanisms, they are interrelated as the ST traffic class schedule influences the latency of AVB traffic. In this paper, we propose a method for the integration of the ST schedule synthesis with an analysis for the AVB class featuring IEEE 802.1Qbu frame preemption under different configurations to reduce the interference between the two classes. We first present a new worst-case response-time (WCRT) analysis for the AVB traffic class in TSN networks with preemption, considering an arbitrary number of AVB queues and different configurations for the CBS credit behavior. Then, we integrate the creation of ST schedule tables with the schedulability analysis of AVB traffic using a heuristic algorithm featuring frame preemption and a novel routing mechanism aimed at maximizing AVB schedulability. Finally, we evaluate our approach using both real-world and synthetic use cases showing the efficiency both in terms of schedule creation runtime and in terms of increasing the schedulability of lower-priority AVB traffic.
18.	Berisa, Aldin, et al. (författare) Comparative Evaluation of Various Generations of Controller Area Network Based on Timing Analysis 2023 Ingår i: IEEE Int. Conf. Emerging Technol. Factory Autom., ETFA. - : Institute of Electrical and Electronics Engineers Inc.. - 9798350339918 Konferensbidrag (refereegranskat)abstract This paper performs a comparative evaluation of various generations of Controller Area Network (CAN), including the classical CAN, CAN Flexible Data-Rate (FD), and CAN Extra Long (XL). We utilize response-time analysis for the evaluation. In this regard, we identify that the state of the art lacks the response-time analysis for CAN XL. Hence, we discuss the worst-case transmission times calculations for CAN XL frames and incorporate them to the existing analysis for CAN to support response-time analysis of CAN XL frames. Using the extended analysis, we perform a comparative evaluation of the three generations of CAN by analyzing an automotive industrial use case. In crux, we show that using CAN FD is more advantageous than the classical CAN and CAN XL when using frames with payloads of up to 8 bytes, despite the fact that CAN XL supports higher bit rates. For frames with 12-64 bytes payloads, CAN FD performs better than CAN XL when running at the same bit rate, but CAN XL performs better when running at a higher bit rate. Additionally, we discovered that CAN XL performs better than the classical CAN and CAN FD when the frame payload is over 64 bytes, even if it runs at the same or higher bit rates than CAN FD.
19.	Berisa, Aldin, et al. (författare) Investigating and Analyzing CAN-to-TSN Gateway Forwarding Techniques 2023 Ingår i: Proc. - IEEE Int. Symp. Real-Time Distrib. Comput., ISORC. - : Institute of Electrical and Electronics Engineers Inc.. - 9798350339024 ; , s. 136-145 Konferensbidrag (refereegranskat)abstract Controller Area Network (CAN) and Ethernet network are expected to co-exist in automotive industry as Ethernet provides a high-bandwidth communication, while CAN is a legacy cost-effective solution. Due to the shortcomings of conventional switched Etherent, such as determinism, IEEE Time Sensitive Networking (TSN) task group developed a set of standards to enhance the switched Ethernet technology providing low-jitter and deterministic communication. Considering these two network domains, we investigate various design approaches for a gateway that connects a CAN domain to a TSN domain. We present three gateway forwarding techniques and we develop end-to-end delay analysis methods for them. Via the analysis methods and applying them to synthetic use cases we show that the intuitive existing approach of encapsulating multiple CAN frames into a single Ethernet frame is not necessarily an efficient solution. In fact, we demonstrate several cases where it is preferable to encapsulate only one CAN frame into a TSN frame, in particular when we use a high speed TSN network. The results have a significant impact on developing such gateways as the implementation of the one-to-one frame encapsulation is considerably simpler than other complex gateway-forwarding techniques.
20.	Bidgoli, Ali M., et al. (författare) NeuroPIM : Felxible Neural Accelerator for Processing-in-Memory Architectures 2023 Ingår i: Proceedings - 2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2023. - : Institute of Electrical and Electronics Engineers Inc.. - 9798350332773 ; , s. 51-56 Konferensbidrag (refereegranskat)abstract The performance of microprocessors under many modern workloads is mainly limited by the off-chip memory bandwidth. The emerging process-in-memory paradigm present a unique opportunity to reduce data movement overheads by moving computation closer to memory. State-of-the-art processing-in-memory proposals stack a logic layer on top of one or multiple memory layers in a 3D fashion and leverage the logic layer to build near-memory processing units. Such processing units are either application-specific accelerators or general-purpose cores. In this paper, we present NeuroPIM, a new processing-in-memory architecture that uses a neural network as the memory-side general-purpose accelerator. This design is mainly motivated by the observation that in many real-world applications, some program regions, or even the entire program, can be replaced by a neural network that is learned to approximate the program's output. NeuroPIM benefits from both the flexibility of general-purpose processors and superior performance of application-specific accelerators. Experimental results show that NeuroPIM provides up to 41% speedup over a processor-side neural network accelerator and up to 8x speedup over a general-purpose processor.
21.	Dabiri, Bita, et al. (författare) Network-on-ReRAM for Scalable Processing-in-Memory Architecture Design 2021 Ingår i: Proceedings - 2021 24th Euromicro Conference on Digital System Design, DSD 2021. - 9781665427036 ; , s. 143-149 Konferensbidrag (refereegranskat)abstract The non-volatile metal-oxide resistive random access memory (ReRAM) is an emerging alternative for the current memory technologies. The unique capability of ReRAM to perform analog and digital arithmetic and logic operations has enabled this technology to incorporate both computation and memory capabilities on the same unit. Due to this interesting property, there is a growing trend in recent years to implement emerging data-intensive applications on ReRAM structures. A typical ReRAM-based processing-in-memory architecture may consist tens to hundreds of ReRAM units (mats) that can either store or process data. To support such large-scale ReRAM structure, this paper proposes a scalable network-on-ReRAM architecture. The proposed network employs a novel associative router architecture, designed based on the ReRAM-based content-addressable memories. With the in-memory packet processing capability, this router yields higher throughput and resource utilization levels than a conventional router. This router is technology compatible with ReRAM and as our evaluations show, employing it to build a network-on-ReRAM makes the emerging ReRAM-based processing-in-memory architectures more scalable and performance-efficient.
22.	Daneshtalab, Masoud, et al. (författare) A New Fair Dynamic Routing Algorithm for Avoiding Hot Spots in NoCs 2006 Ingår i: 2006 International Symposium on Communications and Information Technologies,Vols 1-3. ; , s. 237-241 Konferensbidrag (refereegranskat)abstract This model takes advantage of output selection based on Congestion condition of neighboring switches and input selection based on Weighted Round Robin algorithm which allows packets to be serviced from each input port according to its congestion status that generated by Congestion Aware Routing Selection (CARS) module. The proposed algorithin is fair and starvation free. The simulation results show that the proposed algorithm has lower average delays and lower average peak power compared to previously proposed models.
23.	Daneshtalab, Masoud, et al. (författare) In-order delivery approach for 2D and 3D NoCs 2015 Ingår i: Journal of Supercomputing. - : Springer Science and Business Media LLC. - 0920-8542 .- 1573-0484. ; 71:8, s. 2877-2899 Tidskriftsartikel (refereegranskat)abstract In many applications, it is critical to guarantee the in-order delivery of requests from the master cores to the slave cores, so that the requests can be executed in the correct order without requiring buffers. Since in NoCs packets may use different paths and on the other hand traffic congestion varies on different routes, the in-order delivery constraint cannot be met without support. To guarantee the in-order delivery, traditional approaches either use dimension-order routing or employ reordering buffers at network interfaces. Dimension-order routing degrades the performance considerably while the usage of reordering buffers imposes large area overhead. In this paper, we present a mechanism allowing packets to be routed through multiple paths in the network, helping to balance the traffic load while guaranteeing the in-order delivery. The proposed method combines the advantages of both deterministic and adaptive routing algorithms. The simple idea is to use different deterministic algorithms for independent flows. This approach neither requires reordering buffers nor limits packets to use a single path. The algorithm is simple and practical with negligible area overhead over dimension-order routing. The concept is investigated in both 2D and 3D mesh networks.
24.	Daneshtalab, Masoud, et al. (författare) Introduction to the Special Issue on Network-on-Chip Architectures 2014 Ingår i: Computers & electrical engineering. - : Elsevier BV. - 0045-7906 .- 1879-0755. ; 40:8, s. 257-259 Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
25.	Daneshtalab, Masoud, et al. (författare) Introduction to the special issue on NoC-based many-core architectures 2015 Ingår i: Computers & electrical engineering. - : Elsevier. - 0045-7906 .- 1879-0755. ; 45, s. 359-361 Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
26.	Daneshtalab, Masoud, et al. (författare) On-chip parallel and network-based systems Preface 2015 Ingår i: Integration. - : Elsevier BV. - 0167-9260 .- 1872-7522. ; 50, s. 137-138 Tidskriftsartikel (refereegranskat)
27.	Daneshtalab, Masoud, et al. (författare) Special Issue on Emerging Many-Core Systems for Exascale Computing 2015 Ingår i: ACM Journal on Emerging Technologies in Computing Systems. - : Association for Computing Machinery (ACM). - 1550-4832 .- 1550-4840. ; 11:4 Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
28.	Daneshtalab, Masoud, et al. (författare) Special issue on many-core embedded systems 2014 Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 38:6, s. 525-525 Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
29.	Daneshtalab, Masoud, et al. (författare) Special issue on on-chip parallel and network-based systems 2015 Ingår i: Computing. - : Springer Science and Business Media LLC. - 0010-485X .- 1436-5057. ; 97:6, s. 539-541 Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
30.	Daneshtalab, Masoud, et al. (författare) Special section on design for resilience in cyber-physical systems 2018 Ingår i: CSI International Symposium on Real-Time and Embedded Systems and Technologies, RTEST 2018. - : Institute of Electrical and Electronics Engineers (IEEE). Konferensbidrag (refereegranskat)
31.	Dytckov, Sergei, et al. (författare) Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks 2014 Ingår i: 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD). - 9781479957934 ; , s. 496-503 Konferensbidrag (refereegranskat)abstract Spiking neural networks (SNNs) are the closest approach to biological neurons in comparison with conventional artificial neural networks (ANN). SNNs are composed of neurons and synapses which are interconnected with a complex pattern. As communication in such massively parallel computational systems is getting critical, the network-on-chip (NoC) becomes a promising solution to provide a scalable and robust interconnection fabric. However, using NoC for large-scale SNNs arises a trade-off between scalability, throughput, neuron/router ratio (cluster size), and area overhead. In this paper, we tackle the trade-off using a clustering approach and try to optimize the synaptic resource utilization. An optimal cluster size can provide the lowest area overhead and power consumption. For the learning purposes, a phenomenon known as spike-timing-dependent plasticity (STDP) is utilized. The micro-architectures of the network, clusters, and the computational neurons are also described. The presented approach suggests a promising solution of integrating NoCs and STDP-based SNNs for the optimal performance based on the underlying application.
32.	Dytckov, S., et al. (författare) Exploring NoC jitter effect on simulation of spiking neural networks 2014 Ingår i: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014. - 9781479953134 ; , s. 693-696 Konferensbidrag (refereegranskat)abstract The major bottleneck in simulation of large-scale neural networks is the communication problem due to one-to-many neuron connectivity. Network-on-Chip concept has been proposed to address the problem. This work explores the drawback that is introduced by interconnection networks - a delay jitter. The preliminary experiment is held in the spiking neural network simulator introducing variable communicational delay to the simulation. The performance degradation is reported.
33.	Ebrahimi, Masoumeh, et al. (författare) A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks 2018 Ingår i: IEEE Micro. - : IEEE Computer Society. - 0272-1732 .- 1937-4143. ; 38:3, s. 79-85 Tidskriftsartikel (refereegranskat)abstract For the past three decades, the interconnection network has been developed based on two major theories, one by Dally and the other by Duato. In this article, we introduce EbDa with a simplified theoretical basis, which directly allows for designing an acyclic channel dependency graph and verifying algorithms on their freedom from deadlock. EbDa is composed of three theorems that enable extracting all allowable turns without dealing with turn models.
34.	Ebrahimi, Masoumeh, et al. (författare) A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers 2013 Ingår i: Computing. - : Springer Science and Business Media LLC. - 0010-485X .- 1436-5057. ; 97, s. 631-648 Tidskriftsartikel (refereegranskat)abstract Faults at either the link or router level may result in the failure of the system. Fault-tolerant routing algorithms attempt to tolerate faults by rerouting packets around the faulty region. This rerouting would be at the cost of significant performance loss. The proposed algorithm in this paper is able to tolerate both faulty routers and links with negligible impact on the performance. In fact, the proposed algorithm avoids taking unnecessary longer paths and the shortest paths are always taken as long as a path exists. On the other hand, fault-tolerant routing algorithms might be based on deterministic routing in which all packets use a single path between each pair of source and destination routers. Using deterministic routing, packets reach the destination in the same order they have been delivered from the source so that no reordering buffer is needed at the destination. For improving the performance, fault-tolerant algorithms might be based on adaptive routing in which packets are delivered through multiple paths to destinations. In this case, packets should be reordered at the destinations demanding reordering buffers. The proposed algorithm can be configured in both working modes, such that it can be based on deterministic or adaptive routing.
35.	Ebrahimi, Masoumeh, et al. (författare) EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks 2017 Ingår i: In Proceedings of ISCA ’17. - New York, NY, USA : ACM Press. ; , s. 1-13, s. 703-715 Konferensbidrag (refereegranskat)abstract Freedom from deadlock is one of the most important issues whendesigning routing algorithms in on-chip/off-chip networks. Manyworks have been developed upon Dally’s theory proving that a networkis deadlock-free if there is no cyclic dependency on the channeldependency graph. However, finding such acyclic graph has beenvery challenging, which limits Dally’s theory to networks with a lownumber of channels. In this paper, we introduce three theorems thatdirectly lead to routing algorithms with an acyclic channel dependencygraph.We also propose the partitioning methodology, enablinga design to reach the maximum adaptiveness for the n-dimensionalmesh and k-ary n-cube topologies with any given number of channels.In addition, deadlock-free routing algorithms can be derivedranging from maximally fully adaptive routing down to deterministicrouting. The proposed theorems can drastically remove thedifficulties of designing deadlock-free routing algorithms.
36.	Ebrahimi, Masoumeh, et al. (författare) Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy 2013 Ingår i: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013. ; , s. 1601-1604 Konferensbidrag (refereegranskat)abstract While Networks-on-Chip (NoC) have been increasing in popularity with industry and academia, it is threatened by the decreasing reliability of aggressively scaled transistors. In this paper, we address the problem of faulty elements by the means of routing algorithms. Commonly, fault-tolerant algorithms are complex due to supporting different fault models while preventing deadlock. When moving from 2D to 3D network, the complexity increases significantly due to the possibility of creating cycles within and between layers. In this paper, we take advantages of the Hamiltonian path to tolerate faults in the network. The presented approach is not only very simple but also able to support almost all one-faulty unidirectional links in 2D and 3D NoCs.
37.	Ebrahimi, Masoumeh, et al. (författare) In-Order Delivery Approach for 3D NoCs 2013 Ingår i: 2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013). - : IEEE. - 9781479905621 ; , s. 87- Konferensbidrag (refereegranskat)abstract Routing algorithms can be classified into deterministic and adaptive methods. In deterministic methods, a single path is selected for each pair of source and destination nodes, and thus they are unable to distribute the traffic load over the network. Using deterministic routing, packets reach a destination in the same order they are delivered from a source node. Adaptive routing algorithms can greatly improve the performance by distributing packets over different routes. However, it requires a mechanism to reorder packets at destinations. Thereby, a large reordering buffer and a complex control mechanism are required at each node. This motivated us to propose a method guaranteeing in-order delivery while sending packets through alternative paths. The proposed method combines the advantages of both deterministic and adaptive routing algorithms. We introduce several routing algorithms working together in the network without creating cycles. By using these algorithms, packets of different flows use different routes while packets belonging to the same flow follow a single path. In this way, traffic is distributed over the network while addressing in-order delivery. We employ this approach on three-dimensional Networks-on-Chip.
38.	Ebrahimi, Masoumeh, et al. (författare) NoD : Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in 2.5D ICs 2017 Ingår i: 2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS). - : IEEE. - 9781538643792 ; , s. 28-33 Konferensbidrag (refereegranskat)abstract Due to a high cost of 3D IC process technology, the semiconductor industry is targeting 2.5D ICs with interposer as a fast and low-cost alternative to integrate dissimilar technologies. In this paper, we propose an independent network-on-chip die, called Network-on-Die (NoD), for 2.5D ICs that operates as a communication backbone for heterogeneous many-core systems on interposer. NoD is responsible for routing packets from a source router to a destination router, and the connections between routers and cores pass through the interposer. This technique eliminates the complexity of the routing algorithms in heterogeneous systems by turning the irregular form of NoC in 2.5D ICs into a regular/optimized one in NoD. The performance evaluation is verified through RTL simulations for a heterogeneous many-core system of varying die sizes and with asymmetric shapes. We provide the theoretical justification for our simulation results.
39.	Ebrahimi, Masoumeh, et al. (författare) Partitioning methods for unicast/multicast traffic in 3D NoC architecture 2010 Ingår i: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 127-132 Konferensbidrag (refereegranskat)abstract As the scale of integration grows, the interconnection problem becomes one of the major design considerations of Multi Processor System on Chip (MPSoC). In recent years, many researchers have conducted studies on 3D IC designs stacking multiple layers on top of each other. In order to decrease the transmission delay of unicast/multicast messages in a network based multicore system, the network is divided into several partitions. In this paper, we first introduce a novel idea of balanced partitioning that allows the network to be partitioned effectively. Then, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method based on the idea of balanced partitioning to provide a high degree of parallelism with a considerable reduction of packet delay in unicast/multicast traffic. Simulations are provided to evaluate and compare the performance of proposed methods.
40.	Ebrahimi, Masoumeh, et al. (författare) Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing 2014 Ingår i: IEEE Transactions on Computers. - 0018-9340 .- 1557-9956. ; 63:3, s. 718-733 Tidskriftsartikel (refereegranskat)abstract Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in ChipMultiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and invarious parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at thehardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs,each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore theefficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose theMinimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show thatan advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the networkuntil all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsetsand the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performanceimprovement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent averageand 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.
41.	Ebrahimi, Masoumeh, et al. (författare) Performance Analysis of 3D NoCs Partitioning Methods 2010 Ingår i: IEEE Annual Symposium on VLSI, ISVLSI 2010. ; , s. 479-480 Konferensbidrag (refereegranskat)abstract 3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chlp (NoCs). In this work, several unlcast/multicast partitioning methods are explained in order to And an advantageous method with low communication latency. Moreover, two factors of efficiency, unicast latency and multicast latency, are analyzed by analytical models. We also perform simulation to compare the efficiency of proposed methods. The results show that Mixed Partitioning method outperforms other methods in term of latency.
42.	Ebrahimi, Masoumeh, et al. (författare) Rescuing healthy cores against disabled routers 2014 Konferensbidrag (refereegranskat)abstract A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.
43.	Ebrahimi, Zahra, et al. (författare) A Review on Deep Learning Methods for ECG Arrhythmia Classification 2020 Ingår i: Expert systems with applications. - : Elsevier BV. - 0957-4174 .- 1873-6793 .- 2590-1885. ; 7 Tidskriftsartikel (refereegranskat)abstract Deep Learning (DL) has recently become a topic of study in different applications including healthcare, in which timely detection of anomalies on Electrocardiogram (ECG) can play a vital role in patient monitoring. This paper presents a comprehensive review study on the recent DL methods applied to the ECG signal for the classification purposes. This study considers various types of the DL methods such as Convolutional Neural Network (CNN), Deep Belief Network (DBN), Recurrent Neural Network (RNN), Long Short-Term Memory (LSTM), and Gated Recurrent Unit (GRU). From the 75 studies reported within 2017 and 2018, CNN is dominantly observed as the suitable technique for feature extraction, seen in 52% of the studies. DL methods showed high accuracy in correct classification of Atrial Fibrillation (AF) (100%), Supraventricular Ectopic Beats (SVEB) (99.8%), and Ventricular Ectopic Beats (VEB) (99.7%) using the GRU/LSTM, CNN, and LSTM, respectively
44.	Fallah, Mohammad K., et al. (författare) A symbiosis between population based incremental learning and LP-relaxation based parallel genetic algorithm for solving integer linear programming models 2024 Ingår i: Computing. - : Springer Science and Business Media LLC. - 0010-485X .- 1436-5057. Tidskriftsartikel (refereegranskat)abstract Solving Integer Linear Programming (ILP) models generally lies in the category of NP-hard problems and finding the optimal answer for large models is a computational challenge. Genetic algorithms are a family of metaheuristic algorithms capable of adjusting and redesigning parameters and operations according to the characteristics of ILP models. On the other hand, still the genetic algorithm performs a lot of operations to solve large models, and parallel processing is a suitable technique to tackle this problem. This paper introduces an LP-Relaxation based parallel genetic algorithm that uses a population-based incremental learning technique to presents an expandable solver for large ILP models derived from a behavioral synthesis of digital circuits. In the proposed algorithm, each chromosome provides a state subspace of possible solutions, and each generation is produced based on a probability vector as well as elitism. Our experiments verify the efficiency of the proposed algorithm on multicore platforms, as it outperformed four previous genetic algorithms for solving mixed integer programming problems. The proposed genetic algorithm solved 20 ILP models include up to 5183 int / binary decision variables in less than 20 min using four 16-core AMD Opteron 6386 SE processors. Also, the results indicate that for models with more than 4000 variables, the speedup and the efficiency of the proposed parallel genetic algorithm on 60 CPU cores is more than 18X and 30%, respectively.
45.	Fallah, M. K., et al. (författare) Scalable parallel genetic algorithm for solving large integer linear programming models derived from behavioral synthesis 2020 Ingår i: Proceedings - 2020 28th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2020. - : Institute of Electrical and Electronics Engineers Inc.. - 9781728165820 ; , s. 390-394 Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract Solving Integer Linear Programming (ILP) models generally lies in the category of NP-hard problems. Therefore, as the size of ILP models grows, the efficiency of exact algorithms for solving the models reduced significantly and for large models it is not possible to have the result. Genetic Algorithm (GA) is a metaheuristic method capable of adjusting and redesigning parameters and operations according to the characteristics of ILP models. Still GA has huge search space for large models and parallelization is a suitable technique to tackle this problem. This paper presents a scalable parallel GA to solve large ILP models derived from behavioral synthesis of digital circuits. We show that although models have non-binary variables, only binary variables are sufficient for coding chromosomes. We also use 'unknown' values for some genes to decrease the likelihood of inconsistency in the encoded constraints. Our experiments verify the efficiency and scalability of the proposed algorithm on multicore platforms. The proposed method outperforms IBM ILOG CPLEX 12.6 and MI-LXPM algorithm where the ILP models include 550 to 2258 int / binary decision variables. Also, the results indicate that the saturation point of using parallel processing elements for solving the large ILP models is at least 60.
46.	Farahnakian, Fahimeh, et al. (författare) Adaptive Load Balancing in Learning-based Approaches for Many-core Embedded Systems 2014 Ingår i: Journal of Supercomputing. - : Springer Science and Business Media LLC. - 0920-8542 .- 1573-0484. ; 68:3, s. 1214-1234 Tidskriftsartikel (refereegranskat)abstract Adaptive routing algorithms improve network performance by distributingtraffic over the whole network. However, they require congestion information to facilitateload balancing. To provide local and global congestion information, we proposea learning method based on dual reinforcement learning approach. This informationcan be dynamically updated according to the changing traffic condition in the networkby propagating data and learning packets. We utilize a congestion detection methodwhich updates the learning rate according to the congestion level. This method calculatesthe average number of free buffer slots in each switch at specific time intervalsand compares it with maximum and minimum values. Based on the comparison result,the learning rate sets to a value between 0 and 1. If a switch gets congested, the learningrate is set to a high value, meaning that the global information is more important thanlocal. In contrast, local is more emphasized than global information in non-congestedswitches. Results show that the proposed approach achieves a significant performanceimprovement over the traditional Q-routing, DRQ-routing, DBAR and Dynamic XYalgorithms.
47.	Farahnakian, Fahimeh, et al. (författare) Bi-LCQ: A Low-weight Clustering-based Q-learning Approach for NoCs 2014 Ingår i: Microprocessors and microsystems. - : Elsevier BV. - 0141-9331 .- 1872-9436. ; 38:1, s. 64-75 Tidskriftsartikel (refereegranskat)abstract Network congestion has a negative impact on the performance of on-chip networks due to the increasedpacket latency. Many congestion-aware routing algorithms have been developed to alleviate trafficcongestion over the network. In this paper, we propose a congestion-aware routing algorithm basedon the Q-learning approach for avoiding congested areas in the network. By using the learning method,local and global congestion information of the network is provided for each switch. This information canbe dynamically updated, when a switch receives a packet. However, Q-learning approach suffers fromhigh area overhead in NoCs due to the need for a large routing table in each switch. In order to reducethe area overhead, we also present a clustering approach that decreases the number of routing tablesby the factor of 4. Results show that the proposed approach achieves a significant performance improvementover the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms.
48.	Firuzan, A., et al. (författare) Reconfigurable communication fabric for efficient implementation of neural networks 2015 Ingår i: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467379427 Konferensbidrag (refereegranskat)abstract Handling heavy multicast-based inter-neuron communication is the most challenging issue in parallel implementation of neural networks. To address this problem, a reconfigurable Network-on-Chip (NoC) architecture for neural networks is presented in this paper. The NoC consists of a number of node clusters with a fix topology connected by a reconfigurable inter-cluster communication fabric that efficiently handles multicast communication. The evaluation results show that the proposed architecture can better manage the multicast-based traffic of neural networks than the mesh-based topologies proposed in prior work. It offers up to 60% and 22% lower average message latency compared to a baseline and a state-of-the-Art NoC for neural networks, respectively, which directly translates to faster neural processing.
49.	Firuzan, A., et al. (författare) Reconfigurable Network-on-Chip for 3D Neural Network Accelerators 2018 Ingår i: 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018. - : Institute of Electrical and Electronics Engineers Inc.. - 9781538648933 Konferensbidrag (refereegranskat)abstract Parallel hardware accelerators for large-scale neural networks typically consist of several processing nodes, arranged as a multi- or many-core system-on-chip, connected by a network-on-chip (NoC). Recent proposals also benefit from the emerging 3D memory-on-logic architectures to provide sufficient bandwidth for neural networks. Handling the heavy traffic between neurons and memory and also the multicast-based inter-neuron traffic, which often varies over time, is the most challenging design consideration for the networks-on-chip in such accelerators. To address these issues, a reconfigurable network-on-chip architecture for 3D memory-on-logic neural network accelerators is presented in this paper. The reconfigurable NoC can adapt its topology to the on-chip traffic patterns. It can be also configured as a tree-like structure to support multicast-based neuron-to-neuron and memory-to-neuron traffic of neural networks. The evaluation results show that the proposed architecture can better manage the multicast-based traffic of neural networks than some state-of-the-art topologies and considerably increase throughput and power efficiency.
50.	Forsberg, Håkan, et al. (författare) Challenges in using neural networks in safety-critical applications 2020 Ingår i: AIAA/IEEE Digital Avionics Systems Conference - Proceedings. - : Institute of Electrical and Electronics Engineers Inc.. - 9781728198255 Konferensbidrag (refereegranskat)abstract In this paper, we discuss challenges when using neural networks (NNs) in safety-critical applications. We address the challenges one by one, with aviation safety in mind. We then introduce a possible implementation to overcome the challenges. Only a small portion of the solution has been implemented physically and much work is considered as future work. Our current understanding is that a real implementation in a safety-critical system would be extremely difficult. Firstly, to design the intended function of the NN, and secondly, designing monitors needed to achieve a deterministic and fail-safe behavior of the system. We conclude that only the most valuable implementations of NNs should be considered as meaningful to implement in safety-critical systems.

Skapa referenser, mejla, bekava och länka

Länka till träfflistan

Träfflista för sökning "WFRF:(Daneshtalab Masoud) "

Avgränsa träffmängd

År