| 1. |
- Dasalukunte, Deepak, et al.
(författare)
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A 0.8mm2 9.6mW Implementation of a Multicarrier Faster-Than-Nyquist Signaling Iterative Decoder in 65nm CMOS
- 2012
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Ingår i: [Host publication title missing]. - 1930-8833. - 9781467322126 ; , s. 173-176
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Konferensbidrag (refereegranskat)abstract
- This paper presents a decoder for multi-carrier modulated signals employing Faster-than-Nyquist (FTN) signaling. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65nm CMOS process and occupies an area of 0.8mm2, with a power consumption of 9.6mW at 1.2V when clocked at 100MHz. To the best of our knowledge, those measurement results are from the first-ever silicon implementation of a decoder for FTN signaling.
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| 2. |
- Dasalukunte, Deepak, et al.
(författare)
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A generic hardware MAC for wireless personal area network platforms
- 2008
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Konferensbidrag (refereegranskat)abstract
- This paper presents a generic hardware-MAC for systems designed based on high rate (IEEE 802.15.3) and low rate (IEEE 802.15.4)Wireless Personal Area Networks. functionality that are better run in hardware are moved over from the software part of the MAC layer. An easy to access memory like interface has been defined for data and control transfer between the software and hardware parts of theMAC layer. A key challenge in designing such a system was to arrive at a generic architecture without compromising with either of the standards on the lines of which the two systems are implemented. Emphasis on reuse of the modules has been done in order to avoid repetition of design and implementation effort and in turn reducing the time required for testing. The design has been successfully tested on different FPGA platforms.
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| 3. |
- Dasalukunte, Deepak, et al.
(författare)
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A Transmitter Architecture for Faster-than-Nyquist Signaling Systems
- 2009
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Ingår i: Proceedings, IEEE International Symposium on Circuits and Systems, 2009. - 9781424438273 ; , s. 1028-1031
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Konferensbidrag (refereegranskat)abstract
- This paper presents the complexity analysis of a transmitter architecture for a faster-than-Nyquist (FTN) system. Complexity issues in terms of computations and memory requirements to achieve an FTN system are dealt with. An OFDM based multi-carrier system is considered as it is one of the most widely used in upcoming wireless standards. Retaining the modules within the OFDM transmitter helps in exploiting the already optimized and hardware efficient structures, the IFFT being one. From an implementation perspective the introduction of FTN introduces negligible overhead for the transmitter.
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| 4. |
- Dasalukunte, Deepak, et al.
(författare)
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An 0.8-mm(2) 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS
- 2013
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Ingår i: IEEE Journal of Solid-State Circuits. - 0018-9200. ; 48:7, s. 1680-1688
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents an iterative decoder for faster-than-Nyquist (FTN) and orthogonal signaling multi-carrier systems. FTN signaling is a method of improving bandwidth efficiency at the expense of higher processing complexity in the transceiver. The decoder can switch between orthogonal and FTN signaling modes and exploits channel properties to improve bandwidth efficiency. The decoder is fabricated in a 65-nm CMOS process and occupies a total area of 0.8 mm(2) with decoder core taking up 0.567 mm(2). The power consumption of the chip is 9.6 mW at 1.2 V when clocked at 100 MHz, providing a peak information throughput of 1 Mbps and with an energy efficiency of 0.6 nJ per bit per iteration. To the best of our knowledge, those measurement results are from the first ever silicon implementation of a decoder for FTN signaling.
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| 5. |
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| 6. |
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| 7. |
- Dasalukunte, Deepak, et al.
(författare)
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Complexity analysis of IOTA filter architectures in Faster-than-Nyquist multicarrier systems
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144
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Konferensbidrag (refereegranskat)abstract
- This paper has evaluated the overhead requirements for IOTA pulse shaping filters employed in faster-than-Nyquist multicarrier systems. Faster-than-Nyquist signaling has shown the promise of improving bandwidth efficiency, but comes at the cost of increased processing complexity in the transceiver. The IOTA filter being one of the blocks contributing for the processing overhead, different architectural options have been evaluated. A comparison is drawn between the architectures of the IOTA filter and the suitable architecture with moderate hardware overhead is chosen for implementation.
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| 8. |
- Dasalukunte, Deepak, et al.
(författare)
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Coprocessor accelerated OpenMAX MP3 decoder
- 2006
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- This thesis evaluates the feasibility of designing a coprocessor to accelerate multimedia functions in the OpenMAX standard. OpenMAX is a new standard from the Khronos group, a member funded industry consortium, to integrate the most popular multimedia functions like MP3, MPEG-4 and H.264 under one roof. It provides royalty-free API that helps in developing and/or accelerating the specified standards on a wide variety of platforms and devices. The MP3 subsection in OpenMAX was implemented for evaluating the standard. A high level simulation model of the system consists of a processor core, cache, memory and coprocessor. The coprocessor provides instruction set extensions for the CPU to accelerate the intended functions and was modeled using SystemC like language. The result is evaluated in terms of the speedup obtained. The MP3 decoding process was accelerated 1.2 times as a result of accelerating the DCT by 4 times. The simulations further established the importance of avoiding memory access bottlenecks. The silicon area of the coprocessor was estimated to be half of the original specification limit.
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| 9. |
- Dasalukunte, Deepak, et al.
(författare)
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Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier systems
- 2011
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Ingår i: [Host publication title missing]. - 2159-3477. ; , s. 359-360
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Konferensbidrag (refereegranskat)abstract
- Abstract in UndeterminedFaster-than-Nyquist (FTN) signaling is a method of improving bandwidth efficiency by transmitting information beyond Nyquist's orthogonality limit for interference free transmission. Previously have theoretically established that FTN can provide improved bandwidth efficiency. However, this comes at the cost of higher decoding complexity at the receiver. Our work has evaluated multicarrier FTN signaling for its implementation feasibility and complexity overhead compared to the gains in bandwidth efficiency. The work carried out in this research project includes a systems perspective evaluating performance, algorithm hardware tradeoffs and a hardware architecture leading to a silicon implementation of the decoder for FTN signaling. From the systems perspective, co-existence of FTN and OFDM based multicarrier system has been evaluated. OFDM being a part of many existing and upcoming broadband access technologies such as WLAN, LTE, DVB, this analogy is motivated. On the hardware aspect, the proposed architecture can accommodate both OFDM and FTN systems. The processing blocks in transmitter and receiver were designed for reuse and carry out different functions in the transceiver. Furthemore, the hardware could be configured to operate at varying bandwidth efficiencies (by FTN signaling) to exploit the channel conditions. The decoder implementation also considered block sizes and data rates to comply with the 3GPP standard. The decoding is carried out in as few as 8 iterations making it more practical for implementation in power constrained mobile devices. The decoder is implemented in 65nm CMOS process and occupies a total chip area of 0.8mm2.
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| 10. |
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| 11. |
- Dasalukunte, Deepak, et al.
(författare)
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Hardware implementation of mapper for Faster-than-Nyquist signaling transmitter
- 2009
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Ingår i: [Host publication title missing]. - 9781424443109
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Konferensbidrag (refereegranskat)abstract
- This paper presents the implementation of the mapper block in a faster-than-Nyquist (FTN) signaling transmitter. The architecture is Look-Up Table (LUT) based and the complexity is reduced to a few adders and a buffer to store intermediate results. Two flavors of the architecture has been designed and evaluated in this article, one, a register based implementation for the buffer and the other using a Random Access Memory (RAM). The tradeoff between the two is throughput versus area. The register based implementation is fast requiring only one clock cycle to complete the calculation (i.e a read, calculate and write back) for every incoming FTN symbol. However, it becomes prohibitive when systems with large number of sub-carriers (>64) is considered. The RAM based implementation provides a better solution in terms of area with slightly lower throughput. The mapper has been targetted for both FPGA (Xilinx Virtex-II Pro) and ASIC (130nm standard cell CMOS) implementations. The design has been successfully tested on the FPGA and its output verified with the reference MATLAB model.
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| 12. |
- Dasalukunte, Deepak, et al.
(författare)
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Improved memory architecture for multicarrier faster-than-Nyquist iterative decoder
- 2011
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Ingår i: [Host publication title missing]. ; , s. 296-300
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Konferensbidrag (refereegranskat)abstract
- Architectural improvements for a multicarrier faster-than-Nyquist (FTN) decoder are presented in this work. A previously designed FTN decoder has been optimized during implementation, especially with respect to memory considerations to reduce area and power. The memory optimized architecture achieves 28.7% savings in overall chip area and provides 43.8% savings in the estimated power compared to the pre-optimized design. The BER performance tradeoff from one of the memory optimization shows that the degradation is acceptable and can actually provide better performance for certain scenarios. The other memory optimization considers the minimal buffering required within the interference canceller, resulting in memory reduction close to 50% of what was previously reported. The performance from the actual RTL implementation of the FTN decoder is also presented in comparison with the floating and fixed point benchmark performances.
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| 13. |
- Dasalukunte, Deepak
(författare)
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Multicarrier Faster-than-Nyquist Signaling Transceivers: From Theory to Practice
- 2011
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The demand for spectrum resources in cellular systems worldwide has seen a tremendous escalation in the recent past. The mobile phones of today are capable of being cameras taking pictures and videos, able to browse the Internet, do video calling and much more than an yesteryear computer. Due to the variety and the amount of information that is being transmitted the demand for spectrum resources is continuously increasing. Efficient use of bandwidth resources has hence become a key parameter in the design and realization of wireless communication systems. Faster-than-Nyquist (FTN) signaling is one such technique that achieves bandwidth efficiency by making better use of the available spectrum resources at the expense of higher processing complexity in the transceiver. This thesis addresses the challenges and design trade offs arising during the hardware realization of Faster-than-Nyquist signaling transceivers. The FTN system has been evaluated for its achievable performance compared to the processing overhead in the transmitter and the receiver. Coexistence with OFDM systems, a more popular multicarrier scheme in existing and upcoming wireless standards, has been considered by designing FTN specific processing blocks as add-ons to the conventional transceiver chain. A multicarrier system capable of operating under both orthogonal and FTN signaling has been developed. The performance of the receiver was evaluated for AWGN and fading channels. The FTN system was able to achieve 2x improvement in bandwidth usage with similar performance as that of an OFDM system. The extra processing in the receiver was in terms of an iterative decoder for the decoding of FTN modulated signals. An efficient hardware architecture for the iterative decoder reusing the FTN specific processing blocks and realize different functionality has been designed. An ASIC implementation of this decoder was implemented in a 65nm CMOS technology and the implemented chip has been successfully verified for its functionality.
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| 14. |
- Dasalukunte, Deepak, et al.
(författare)
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Multicarrier faster-than-Nyquist transceivers: hardware architecture and performance analysis
- 2011
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Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 58:4, s. 827-838
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Tidskriftsartikel (refereegranskat)abstract
- This paper evaluates the hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient hardware implementation. This work proposes a hardware architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of FFTs for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time-frequency spacing, finite wordlengths and their design trade-offs for reduced complexity iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65nm CMOS and FPGA. From the hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead.
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| 15. |
- Mehmood, Shahid, et al.
(författare)
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Hardware architecture of IOTA pulse shaping filters for multicarrier systems
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers. - 1549-8328. ; 60:3, s. 733-742
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a hardware architecture of pulse shaping filter used in multicarrier systems. The filter can be configured to be used for both transmitter and receiver with limited overhead. Generic implementation complexity analysis for a filter in a multicarrier system with N sub-carriers is presented, while the implemented architecture is for a system with 128 sub-carriers. The pulse shaping filter is part of a larger system based on faster-than-Nyquist signaling and aided in an overall complexity reduction. Hence designing an efficient hardware architecture to keep the overhead moderate was the motivation behind this work. Architectural optimizations has been carried out in order to reduce area and power. The implementation of the proposed hardware architecture was carried out using a 65nm CMOS process. The chip core occupies an area of 0.11mm2 and is estimated to consume 14.4mW of power when running at 200MHz.
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| 16. |
- Noguet, Dominique, et al.
(författare)
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An MC-SS platform for short-range communications in the Personal Network context
- 2008
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Ingår i: Eurasip Journal on Wireless Communications and Networking. - : Springer Science and Business Media LLC. - 1687-1472 .- 1687-1499.
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Tidskriftsartikel (refereegranskat)abstract
- Wireless Personal Area Networks (WPAN) has gained interest in the last few years and several air interfaces have been proposed to cover WPAN applications. A Multi-Carrier Spread Spectrum (MC-SS) air interface specified to achieve 130 Mbps in typical WPAN channels, is presented in this paper. It operates in the 5.2 GHz ISM band and achieves a spectral efficiency of 3.25 b.s-1.Hz-1. Besides the robustness of the MC-SS approach, this air interface yields to reasonable implementation complexity. This paper focuses on the hardware design and prototype of this MC-SS air interface. The prototype includes RF, baseband and IEEE802.15.3 compliant Medium Access Control (MAC) features. Implementation aspects are carefully analyzed for each part of the prototype and key hardware design issues and solutions are presented. Hardware complexity and implementation loss are compared to theoretical expectation, as well as flexibility are discussed. Measurement results are provided for real condition of operations.
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| 17. |
- Nouget, Dominique, et al.
(författare)
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Link level prototypes
- 2010
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Ingår i: My Personal Adaptive Global NET (MAGNET). - Dordrecht : Springer Netherlands. - 1860-4862. - 9789048134366 ; , s. 283-336
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Bokkapitel (refereegranskat)
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