| 1. |
- Abermann, S., et al.
(författare)
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Processing and evaluation of metal gate/high-kappa/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-kappa dielectric
- 2007
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
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Tidskriftsartikel (refereegranskat)abstract
- We evaluate various metal gate/high-K/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
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| 2. |
- Gottlob, H. D. B., et al.
(författare)
-
0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
- 2006
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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| 3. |
- Gottlob, H. D. B., et al.
(författare)
-
CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
- 2006
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
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Tidskriftsartikel (refereegranskat)abstract
- Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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| 4. |
- Gottlob, H D B, et al.
(författare)
-
Introduction of crystalline high-k gate dielectrics in a CMOS process
- 2005
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Ingår i: Journal of Non-Crystalline Solids. - : Elsevier BV. - 0022-3093 .- 1873-4812. ; 351:21-23, s. 1885-1889
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Tidskriftsartikel (refereegranskat)abstract
- In this work we report on methods to introduce crystalline rare-earth (RE) oxides with high (k > 3.9) dielectric constants (high-k) in a CMOS process flow. Key process steps compatible with crystalline praseodymium oxide (Pr2O3) high-k gate dielectric have been developed and evaluated in metal-oxide-semiconductor (MOS) structures and n-MOS transistors fabricated in an adapted conventional bulk process. From capacitance-voltage measurements a dielectric constant of k = 36 has been calculated. Furthermore an alternative process sequence suitable for the introduction of high-k material into silicon on insulator (SOI) MOS-field-effect-transistors (MOSFET) is presented. The feasibility of this process is shown by realization of n- and p-MOSFETs with standard SiO2 gate dielectric as demonstrator. SiO2 gate dielectric can be replaced by crystalline RE-oxides in the next batch fabrication.
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| 5. |
- Wahlbrink, T., et al.
(författare)
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Highly selective etch process for silicon-on-insulator nano-devices
- 2005
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 78-79:SI, s. 212-217
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Tidskriftsartikel (refereegranskat)abstract
- Reactive ion etch (RIE) processes with HBr/O-2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12 nm gate length and optimized photonic devices with ultrahigh Q-factors.
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| 6. |
- Abermann, S., et al.
(författare)
-
Processing and evaluation of metal gate/high-k/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-k dielectric
- 2007
-
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1635-1638
-
Tidskriftsartikel (refereegranskat)abstract
- We evaluate various metal gate/high-k/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.
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| 7. |
- Echtermeyer, T., et al.
(författare)
-
Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes
- 2007
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621
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Tidskriftsartikel (refereegranskat)abstract
- Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
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| 8. |
- Efavi, J K, et al.
(författare)
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Investigation of NiAlN as gate-material for submicron CMOS technology
- 2004
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 76:1-4, s. 354-359
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Tidskriftsartikel (refereegranskat)abstract
- Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.
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| 9. |
- Efavi, J K, et al.
(författare)
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Tungsten work function engineering for dual metal gate nano-CMOS
- 2005
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Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 16:7, s. 433-436
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Tidskriftsartikel (refereegranskat)abstract
- A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.
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| 10. |
- Fuchs, A., et al.
(författare)
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Nanowire fin field effect transistors via UV-based nanoimprint lithography
- 2006
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:6, s. 2964-2967
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Tidskriftsartikel (refereegranskat)abstract
- A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3 sigma). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.
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| 11. |
- Gomeniuk, Y., et al.
(författare)
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Low-temperature conductance measurements of surface states in HfO2-Si structures with different gate materials
- 2006
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Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 9:6, s. 980-984
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Tidskriftsartikel (refereegranskat)abstract
- Metal-oxide-semiconductor capacitors based on HfO2 gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator-semiconductor interface. C-V and G-omega measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180-300 K. From the maximum of the plot G/omega vs. ln(omega) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge. The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2 x 10(11) cm(-2)eV(-1) for Al and up to (3.5-5.5) x 10(12)cm(-2)eV(-1) for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8 x 10(-17)cm(2) at 200 K for Al-HfO2-Si structure.
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| 12. |
- Gottlob, H. D. B., et al.
(författare)
-
Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics
- 2006
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Ingår i: ESSDERC 2006. - 9781424403011 ; , s. 150-153
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Konferensbidrag (refereegranskat)abstract
- Two process concepts for integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
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| 13. |
- Gottlob, H. D. B., et al.
(författare)
-
Investigation of high-K gate stacks with epitaxial Gd(2)O(3) and FUSINiSi metal gates down to CET=0.86 nm
- 2006
-
Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 9:6, s. 904-908
-
Tidskriftsartikel (refereegranskat)abstract
- Novel gate stacks with epitaxial gadoliniurn oxide (Gd(2)O(3)) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10(-7) A cm(-2) are observed at a capacitance equivalent oxide thickness of CET = 1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd(2)O(3) thickness of 3.1 nm yield current densities down to 0.5 A cm(-2) at V(g) = + 1 V. The extracted dielectric constant for these gate stacks ranges from k = 13 to 14. These results emphasize the potential of NiSi/Gd(2)O(3) gate stacks for future material-based scaling of CMOS technology.
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| 14. |
- Gottlob, H D B, et al.
(författare)
-
Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics
- 2006
-
Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:2, s. 710-714
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Tidskriftsartikel (refereegranskat)abstract
- A "gate first" silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10 mu m down to 40 nm on a fully depleted 25 nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100 nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxial high-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.
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| 15. |
- Lemme, Max C., 1970-, et al.
(författare)
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Comparison of metal gate electrodes on MOCVD HfO2
- 2005
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 45:5-6, s. 953-956
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Tidskriftsartikel (refereegranskat)abstract
- Metal gate electrodes of sputtered aluminum (At), titanium nitride (TiN) and nickel aluminum nitride (NiAlN) are investigated in this work. They are compared with respect to their compatibility with metal organic chemical vapor deposited (MOCVD) hafnium dioxide (HfO2) gate dielectrics. TiN, with a midgap work function of 4.65 eV on SiO2, exhibits promising characteristics as metal gate on HfO2. In addition, encouraging results are presented for the ternary metal NiAlN, whereas classic At electrodes are found unstable in conjunction with HfO2.
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| 16. |
- Lemme, Max C., 1970-, et al.
(författare)
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Nanoscale TiN metal gate technology for CMOS integration
- 2006
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1551-1554
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Tidskriftsartikel (refereegranskat)abstract
- A TiN metal gate technology including essential natiostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 degrees C and yield excellent CV and IV characteristics.
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| 17. |
- Schmidt, M., et al.
(författare)
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Nickel-silicide process for ultra-thin-body SOI-MOSFETs
- 2005
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 82:3-4, s. 497-502
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-on-insulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si3N4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80 nm down to 15 nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices.
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